IP Library › Granted Patent US 12,604,598
Granted Patent B2
US 12,604,598 · App. 18/043,969 · Granted Apr 14, 2026

Solid-state imaging device and electronic apparatus

Inventors: Tomoki Hiramatsu (Kanagawa, JP); Hideaki Togashi (Kanagawa, JP); Nobuhiro Kawai (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H10K39/32H10F39/1825H10F39/8027H10F39/8037H10F39/8053H10F39/807H10F39/811
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Quick Facts
Patent No.
US 12,604,598
App. No.
18/043,969
Granted
Apr 14, 2026
Kind
B2
Abstract

The quantum efficiency can be improved. A solid-state imaging device according to an embodiment includes: a plurality of pixels arranged in a matrix, in which each of the pixels includes a first semiconductor layer, a photoelectric conversion section disposed on the first semiconductor layer on a side of a first surface, an accumulation electrode disposed on the first semiconductor layer close to a side of a second surface on a side opposite to the first surface, a wiring extending from the second surface of the first semiconductor layer, a floating diffusion region connected to the first semiconductor layer via the wiring, and a first gate electrode disposed close to the wiring.

Claims (61)

1 . A solid-state imaging device, including:

a plurality of pixels arranged in a matrix, wherein

each of the pixels includes:

a first semiconductor layer;

a photoelectric conversion section disposed above the first semiconductor layer on a side of a first surface of the first semiconductor layer;

an accumulation electrode disposed below the first semiconductor layer close to a side of a second surface of the first semiconductor layer on a side opposite to the first surface of the first semiconductor layer;

a readout electrode, wherein at least a portion of the accumulation electrode is disposed between the readout electrode and the photoelectric conversion section;

a semiconductor wiring extending from the second surface of the first semiconductor layer to the readout electrode, wherein the semiconductor wiring is a part of the first semiconductor layer;

a floating diffusion region connected to the first semiconductor layer via at least the semiconductor wiring and the readout electrode; and

a first gate electrode disposed close to the semiconductor wiring.

2 . The solid-state imaging device according to claim 1 , wherein

the accumulation electrode is disposed closer to the first semiconductor layer than the first gate electrode.

3 . The solid-state imaging device according to claim 1 , wherein

the accumulation electrode and the first gate electrode are disposed on a same plane.

4 . The solid-state imaging device according to claim 1 , wherein

adjacent pixels among the plurality of pixels are connected to a common floating diffusion region.

5 . The solid-state imaging device according to claim 1 , wherein

each of the pixels further includes

a second gate electrode disposed close to the semiconductor wiring at a position closer to the floating diffusion region than the first gate electrode, and

a memory electrode disposed close to the semiconductor wiring at a position between the first gate electrode and the second gate electrode.

6 . The solid-state imaging device according to claim 5 , wherein

the first gate electrode is connected between the plurality of pixels, and

the memory electrode is connected between the plurality of pixels.

7 . The solid-state imaging device according to claim 5 , wherein each of the pixels further includes a second semiconductor layer positioned between the first semiconductor layer and the floating diffusion region,

the semiconductor wiring includes

a first wiring extending from the first semiconductor layer and connected to the second semiconductor layer, and

a second wiring extending from the second semiconductor layer and connected to the floating diffusion region,

the first gate electrode is disposed close to the first wiring,

the memory electrode is disposed close to the second semiconductor layer, and

the second gate electrode is disposed close to the second wiring.

8 . The solid-state imaging device according to claim 1 , wherein

the first gate electrode is disposed at a position surrounding a side surface of the semiconductor wiring.

9 . The solid-state imaging device according to claim 1 , wherein

the accumulation electrode is disposed at a position surrounding a side surface of the semiconductor wiring.

10 . The solid-state imaging device according to claim 1 , wherein

a cross section of the semiconductor wiring is circular or polygonal.

11 . The solid-state imaging device according to claim 1 , wherein

the semiconductor wiring has a tapered shape having diameter decreasing from the first semiconductor layer to the floating diffusion region.

12 . The solid-state imaging device according to claim 1 , wherein

a plurality of on-chip lenses disposed on a side opposite to the first semiconductor layer with respect to the photoelectric conversion section, and

at least one of the plurality of on-chip lenses is disposed to straddle at least two adjacent pixels among the plurality of pixels.

13 . The solid-state imaging device according to claim 1 , wherein

each of the pixels further includes a color filter disposed on a side of a light incident surface of the photoelectric conversion section.

14 . The solid-state imaging device according to claim 1 , wherein

each of the pixels further includes a color filter disposed on a side opposite to the photoelectric conversion section sandwiching the first semiconductor layer.

15 . The solid-state imaging device according to claim 1 , wherein

the photoelectric conversion section is an organic film.

16 . The solid-state imaging device according to claim 1 , wherein

the first semiconductor layer includes

a first layer in contact with the photoelectric conversion section, and

a second layer positioned on a side opposite to the photoelectric conversion section sandwiching the first layer.

17 . The solid-state imaging device according to claim 1 , wherein

each of the pixels further includes a shield electrode disposed at a boundary with an adjacent pixel.

18 . The solid-state imaging device according to claim 1 , wherein

each of the pixels further includes a fixed charge film disposed at a boundary with an adjacent pixel.

19 . The solid-state imaging device according to claim 18 , wherein

the fixed charge film has a same polarity as a polarity of a charge generated by photoelectric conversion by the photoelectric conversion section.

20 . An electronic apparatus, including:

the solid-state imaging device according to claim 1 ;

a lens that forms an image of incident light on the solid-state imaging device; and

a processing circuit that executes predetermined processing on a signal output from the solid-state imaging device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2023
From: HIRAMATSU, TOMOKI; TOGASHI, HIDEAKI; KAWAI, NOBUHIRO
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 062874/0247 →
Priority Claims (1)
JP 2020-161366 · Sep 25, 2020 · national
Continuity (1)
Related Publication 20230403871A1 · Dec 14, 2023
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