IP Library Granted Patent US 12,739,982
Granted Patent B2
US 12,739,982 · App. 18/625,063 · Granted Sep 15, 2026

Methods of forming interconnect circuits methods

Inventors: Kevin Michael Coakley (Belmont, CA); Malcolm Parker Brown (Mountain View, CA); Dongao Yang (Redwood City, CA); Michael Lawrence Miller (San Mateo, CA); Paul Henry Lego (Woodside, CA)
Assignee: CelLink Corporation
H05K3/4623H05K3/007H05K3/0073H05K3/06H05K3/20H05K3/281H01M50/519H05K1/0201H05K1/118H05K3/046H05K3/064H05K3/44H05K3/445H05K2201/0145H05K2201/015H05K2201/0154H05K2201/10037H05K2203/066Y02E60/10Y10T29/49156
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Quick Facts
Patent No.
US 12,739,982
App. No.
18/625,063
Granted
Sep 15, 2026
Kind
B2
Abstract

A method of forming a flexible interconnect circuit is described. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators.

Claims (34)

1 . A method of forming a flexible interconnect circuit for interconnecting battery cells, the method comprising:

laminating a substrate to a conductive layer, wherein:

the conductive layer comprises a first side and a second side, opposite of the first side, and

the substrate is laminated to the second side of the conductive layer;

patterning the conductive layer while the conductive layer remains laminated to the substrate, wherein:

patterning the conductive layer forms pattern openings defining a first conductive portion, a second conductive portion, and a third conductive portion of the conductive layer, and

the third conductive portion is positioned between and separated from each of the first conductive portion and the second conductive portion by the pattern openings extending through the conductive layer but not the substrate;

laminating a first insulator to the first side of the conductive layer while the conductive layer remains laminated to the substrate, wherein the first insulator comprises a first-insulator opening;

removing the substrate from the conductive layer while the first insulator remains laminated to the conductive layer; and

laminating a second insulator to the second side of the conductive layer while the first insulator remains laminated to the conductive layer, wherein:

the third conductive portion is removed before laminating the second insulator,

the second insulator comprises a second-insulator opening,

the first-insulator opening and the second-insulator opening allow access to the conductive layer from each of the first side and the second side, respectively, of the conductive layer, and

at least one of the first insulator and the second insulator comprises a material selected from the group consisting of polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), and polypropylene (PP).

2 . The method of claim 1 , wherein the first insulator comprises the first-insulator opening before laminating the first insulator to the conductive layer.

3 . The method of claim 1 , wherein the second insulator comprises the second-insulator opening before laminating the second insulator to the conductive layer.

4 . The method of claim 1 , wherein the third conductive portion is removed before laminating the first insulator.

5 . The method of claim 1 , wherein the third conductive portion is removed while removing the substrate from the conductive layer.

6 . The method of claim 1 , wherein the third conductive portion is removed after removing the substrate from the conductive layer.

7 . The method of claim 1 , wherein the conductive layer comprises aluminum.

8 . The method of claim 1 , wherein the conductive layer comprises copper.

9 . The method of claim 1 , wherein the conductive layer is a rolled metal foil.

10 . The method of claim 1 , wherein the conductive layer has a thickness of between 50 micrometers and 500 micrometers.

11 . The method of claim 1 , wherein the conductive layer has a thickness of between 10 micrometers and 1,000 micrometers.

12 . The method of claim 1 , wherein the first insulator comprises an insulator adhesive, contacting the conductive layer and comprising one or more of a polyolefin adhesive, a polyester adhesive, a polyimide adhesive, an acrylic, an epoxy, a cross-linking adhesive, a pressure-sensitive adhesive, and a thermoplastic adhesive.

13 . The method of claim 1 , wherein the first insulator comprises an insulator adhesive, contacting the conductive layer and comprising a pressure-sensitive adhesive.

14 . The method of claim 1 , wherein one or both of the first insulator and the second insulator are configured to adhesively bond to one or more external components.

15 . The method of claim 1 , wherein:

the method further comprises positioning an additional conductive portion over the first conductive portion, and

the additional conductive portion and the first conductive portion are interconnected.

16 . The method of claim 15 , wherein the additional conductive portion and the first conductive portion are positioned between the first insulator and the second insulator.

17 . The method of claim 16 , wherein the first insulator and the second insulator are supported relative to each other by an insulator adhesive, extending to the additional conductive portion and the first conductive portion.

18 . The method of claim 1 , wherein patterning the conductive layer at least partially damages the substrate.

19 . The method of claim 1 , wherein patterning the conductive layer is performed using one or more of laser cutting and laser ablation.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2024
From: COAKLEY, KEVIN MICHAEL; BROWN, MALCOIM PARKER; YANG, DONGAO; MILLER, MICHAEL LAWRENCE; LEGO, PAUL HENRY
To: CELLINK CORPORATION
Reel/Frame 067017/0290 →
Continuity (4)
Continuation 17383129 · Jul 22, 2021
Continuation 16034899 · Jul 13, 2018
Provisional Application 62531995 · Jul 13, 2017
Related Publication 20240276632A1 · Aug 15, 2024
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