Clock and data recovery for burst-mode serial signals
View Patent ↗A clock and data recovery device recovers data from a sequential stream of data that includes bursts of data separated by gaps. Each burst of data arrives with its own phase and with its own deviation from a nominal frequency. The bursts of data begin with a preamble that is utilized to determine the timing of the burst. The clock and data recovery device determines the timing of a burst of data using signals from one or more demultiplexers or samplers. At the start of each burst of data, sampled input signals are analyzed by an edge detector to determine a sample phase for the burst. A selector utilizes the sample phase determined by the edge detector to choose which of the sampled input signals to use to produce output data signals from the clock and data recovery device.
1. A clock and data recovery device, comprising:
sampling circuitry configured to receive a serial input signal and produce parallel signals by sampling the serial input signal, where multiple samples are produced for each bit time of the serial input signal;
phasing circuitry coupled to the parallel signals and configured to produce a phase selection signal indicative of the location of a data transition among the parallel signals; and
selection circuitry coupled to the parallel signals and configured to produce at least one signal selected from the parallel signals based on the phase selection signal,
wherein the phasing circuitry is further configured to produce the phase selection signal when a burst signal is active and maintain the phase selection signal when the burst signal is not active.
2. The clock and data recovery device of claim 1 , wherein the sampling circuitry is further configured to produce the parallel signals based on a reference clock signal.
3. The clock and data recovery device of claim 1 , further comprising demultiplexing circuitry coupled to the at least one signal selected by the selection circuitry and configured to produce parallel output signals by demultiplexing the at least one signal selected by the selection circuitry.
4. The clock and data recovery device of claim 1 , further comprising clock generation circuitry configured to receive a reference clock signal and produce a plurality of clock signals at a common frequency and distinct phases.
5. The clock and data recovery device of claim 1 , wherein the sampling circuitry comprises a plurality latches configured to receive the serial input signal and produce the parallel signals, each of the plurality of latches configured to sample the serial input signal at distinct times.
6. The clock and data recovery device of claim 1 , wherein the sampling circuitry comprises: a plurality of deserializers configured to receive the serial input signal and produce the parallel signals, each of the plurality of deserializers configured to sample the serial input signal at distinct times.
7. The clock and data recovery device of claim 6 , further comprising registers configured to couple the outputs of the plurality of deserializers to the phasing circuitry and the selection circuitry.