Clock and data recovery unit without an external reference clock
View Patent ↗A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without use an external reference clock. A reference clock generator supplies a reference clock signal to a clock and data recovery module that uses the reference clock as a tuning or reference signal to produce the recovered clock and recovered data signals. The reference clock generator modifies the reference clock signal so that its frequency corresponds, within a small tolerance, to the data rate of the serial data stream. The reference clock generator determines a beat frequency between a voltage-controlled oscillator clock signal and the data rate and adjusts the voltage-controlled oscillator frequency, from which the reference clock is generated, to lower the beat frequency below a divided down version of the voltage-controlled oscillator clock.
1. A clock and data recovery device, comprising:
reference clock generator circuitry configured to receive a serial data signal and to produce a first clock signal oscillating at a frequency substantially a sub-harmonic of a data rate of the serial data signal without utilizing an external reference clock signal; and
clock and data recovery circuitry configured to receive the serial data signal and the first clock signal and produce the data output signal representing data recovered from the serial data signal and the second clock signal that is synchronous with the data output signal,
wherein the reference clock generator circuitry comprises:
an oscillator configured to supply a third clock signal oscillating at a controlled frequency, wherein the reference clock generator circuitry utilizes the third clock signal to produce the first clock signal;
a beat frequency generator configured to receive the serial data signal and the third clock signal and produce a beat frequency indicator indicating a difference between the data rate of the serial input signal and the frequency of the third clock signal;
a first divider configured to receive the third clock signal and produce an output signal at a lower frequency; and
a frequency difference detector configured to compare a frequency of the output signal of the first divider and the beat frequency indicator and produce a frequency comparison indicator.
2. The clock and data recovery device of claim 1 , wherein the oscillator is further configured to adjust the frequency of the third clock signal based on the frequency comparison indicator.
3. The clock and data recovery device of claim 1 , further comprising a filter configured to filter the frequency comparison indicator and produce a frequency control signal, and
wherein the oscillator is further configured to control the frequency of the third clock signal utilizing the frequency control signal.
4. A clock and data recovery device, comprising:
reference clock generator circuitry configured to receive a serial data signal and to produce a first clock signal oscillating at a frequency substantially a sub-harmonic of a data rate of the serial data signal without utilizing an external reference clock signal; and
clock and data recovery circuitry configured to receive the serial data signal and the first clock signal and produce a data output signal representing data recovered from the serial data signal and a second clock signal that is synchronous with the data output signal;
wherein the reference clock generator circuitry comprises:
an oscillator configured to supply a third clock signal oscillating at a controlled frequency, wherein the reference clock generator circuitry utilizes the third clock signal to produce the first clock signal;
a beat frequency generator configured to receive the serial data signal and the third clock signal and produce a beat frequency indicator indicating a difference between the data rate of the serial input signal and the frequency of the third clock signal;
a first divider configured to receive the third clock signal and produce an output signal at a lower frequency; and
a frequency difference detector configured to compare a frequency of the output signal of the first divider and the beat frequency indicator and produce a frequency comparison indicator; and
a difference signal oscillating at a frequency substantially proportional to the difference between the data rate of the serial data signal and the frequency of the third clock signal; and
an indicator of whether the data rate of the serial data signal or the frequency of the third clock signal is greater.
5. A clock and data recovery device, comprising:
reference clock generator circuitry configured to receive a serial data signal and to produce a first clock signal oscillating at a frequency substantially proportional to a data rate of the serial data signal without utilizing an external reference clock signal; and
clock and data recovery circuitry configured to receive the serial data signal and the first clock signal and produce a data output signal representing data recovered from the serial data signal and a second clock signal that is synchronous with the data output signal;
wherein the reference clock generator circuitry comprises:
an oscillator configured to supply a third clock signal oscillating at a controlled frequency, wherein the reference clock generator circuitry utilizes the third clock signal to produce the first clock signal;
a beat frequency generator configured to receive the serial data signal and the third clock signal and produce a beat frequency indicator indicating a difference between the data rate of the serial input signal and the frequency of the third clock signal;
a first divider configured to receive the third clock signal and produce an output signal at a lower frequency; and
a frequency difference detector configured to compare a frequency of the output signal of the first divider and the beat frequency indicator and produce a frequency comparison indicator; and
wherein the beat frequency indicator comprises:
a fast difference signal oscillating at a frequency substantially proportional to the frequency of the third clock signal minus the data rate of the serial data signal when the frequency of the third clock signal is higher than the data rate of the serial data signal; and
a slow difference signal oscillating at a frequency substantially proportional to the data rate of the serial data signal minus the frequency of the third clock signal when the frequency of the data rate of the serial data signal is higher than the third clock signal.
6. The clock and data recovery device of claim 5 , wherein the beat frequency generator comprises a quadricorrelator.
7. The clock and data recovery device of claim 6 , wherein the third clock signal comprises an in-phase clock signal and a quadrature clock signal, and wherein the quadricorrelator comprises:
a first flip-flop configured to sample the in-phase clock signal on rising edges of the serial data signal to produce an in-phase sample signal;
a second flip-flop configured to sample the quadrature clock signal on rising edges of the serial data signal to produce a quadrature sample signal; and
circuitry configured to generate the fast difference signal and the slow difference signal utilizing the in-phase sample signal and the quadrature sample signal.
8. The clock and data recovery device of claim 7 , wherein the circuitry configured to generate the fast difference signal and slow difference signal comprises:
a mobius circuit configured to shift a signal according to the sequence of the in-phase sample signal and the quadrature sample signal; and
circuitry configured to receive signals from the mobius circuit and produce the slow difference signal that pulses when the data rate of the serial data signal is higher than frequency of the third clock signal and the fast difference signal that pulses when than frequency of the third clock signal is higher the data rate of the serial data signal.
9. A clock and data recovery device, comprising:
reference clock generator circuitry configured to receive a serial data signal and to produce a first clock signal oscillating at a frequency substantially a sub-harmonic of a data rate of the serial data signal without utilizing an external reference clock signal; and
clock and data recovery circuitry configured to receive the serial data signal and the first clock signal and produce a data output signal representing data recovered from the serial data signal and a second clock signal that is synchronous with the data output signal;
wherein the reference clock generator circuitry comprises:
an oscillator configured to supply a third clock signal oscillating at a controlled frequency, wherein the reference clock generator circuitry utilizes the third clock signal to produce the first clock signal;
a beat frequency generator configured to receive the serial data signal and the third clock signal and produce a beat frequency indicator indicating a difference between the data rate of the serial input signal and the frequency of the third clock signal;
a first divider configured to receive the third clock signal and produce an output signal at a lower frequency; and
a frequency difference detector configured to compare a frequency of the output signal of the first divider and the beat frequency indicator and produce a frequency comparison indicator; and
wherein the reference clock generator circuitry further comprises a second divider configured to receive the third clock signal and produce the first clock signal at a lower frequency.
10. A clock and data recovery device, comprising:
reference clock generator circuitry configured to receive a serial data signal and to produce a first clock signal oscillating at a frequency substantially a sub-harmonic of a data rate of the serial data signal without utilizing an external reference clock signal; and
clock and data recovery circuitry configured to receive the serial data signal and the first clock signal and produce a data output signal representing data recovered from the serial data signal and a second clock signal that is synchronous with the data output signal;
wherein the reference clock generator circuitry comprises:
an oscillator configured to supply a third clock signal oscillating at a controlled frequency, wherein the reference clock generator circuitry utilizes the third clock signal to produce the first clock signal;
a beat frequency generator configured to receive the serial data signal and the third clock signal and produce a beat frequency indicator indicating a difference between the data rate of the serial input signal and the frequency of the third clock signal;
a first divider configured to receive the third clock signal and produce an output signal at a lower frequency; and
a frequency difference detector configured to compare a frequency of the output signal of the first divider and the beat frequency indicator and produce a frequency comparison indicator; and
wherein the frequency comparison indicator comprises:
an up comparison signal that signals that the frequency of the third clock signal is less than the data rate of the serial data signal; and
a down comparison signal that signals that the frequency of the third clock signal is greater than the data rate of the serial data signal.
11. The clock and data recovery device of claim 10 , wherein the oscillator is further configured to increase the frequency of the third clock signal when the up comparison signal is active and the down comparison signal is inactive and to decrease the frequency of the third clock signal when the down comparison signal is active and the up comparison signal is inactive.
12. The clock and data recovery device of claim 10 , wherein the frequency difference detector comprises:
a first counter configured to increment on rising edges of the fast difference signal, reset to zero when a reset signal is asserted, and assert an up limit signal when the counter reaches a maximum value;
a second counter configured to increment on rising edges of the slow difference signal, reset to zero when the reset signal is asserted, and assert a down limit signal when the counter reaches the maximum value;
a third counter configured to increment on rising edges of the output signal of the first divider, reset to zero when the reset signal is asserted, and assert a clock limit signal when the counter reaches the maximum value;
logic circuitry configured to assert the reset signal when any of the counters reaches the maximum value; and
circuitry configured to produce the up comparison signal and the down comparison signal utilizing the up limit signal, the down limit signal, and the clock limit signal.
13. The clock and data recovery device of claim 12 , wherein the circuitry configured to produce the up comparison signal and the down comparison signal comprises:
a first set-reset latch configured to set when the clock limit signal is asserted, to reset when either the up limit signal or the down limit signal is asserted, and to produce an unlocked signal that is active when the latch is reset and inactive when the latch is set;
a second set-reset latch configured to set when the up reset signal is asserted and reset when the down reset signal is asserted; and
selection circuitry configured to supply, when the unlocked signal is inactive, the up comparison signal and the down comparison signal having the same value and to supply, when the unlocked signal is active, the up comparison signal that is active when the second set-reset latch is set and inactive when the second set-reset latch is reset and the down comparison signal that is active when the second set-reset latch is reset and inactive when the second set-reset latch is set.
14. A reference clock generator device, comprising:
a controlled oscillator configured to supply a first clock signal oscillating at a controlled frequency and utilized to produce a reference clock signal;
a beat frequency generator configured to receive a serial data signal and the first clock signal and produce a beat frequency indicator indicating a difference between the data rate of the serial data signal and the frequency of the first clock signal;
a first divider configured to receive the first clock signal and produce an output signal at a lower frequency;
a second divider configured to receive the first clock signal and produce the reference clock signal at a lower frequency; and
a frequency difference detector configured to compare a frequency of the output signal of the first divider and the beat frequency indicator and produce a frequency comparison indicator.
15. The reference clock generator device of claim 14 , wherein the oscillator is further configured to adjust the frequency of the first clock signal based on the frequency comparison indicator.
16. The reference clock generator device of claim 14 , further comprising a filter configured to filter the frequency comparison indicator and produce a frequency control signal, and
wherein the oscillator is further configured to control the frequency of the first clock signal utilizing the frequency control signal.
17. The reference clock generator device of claim 14 , wherein the beat frequency indicator comprises:
a fast difference signal oscillating at a frequency proportional to the frequency of the first clock signal minus the data rate of the serial data signal when the frequency of the first clock signal is higher than the data rate of the serial data signal; and
a slow difference signal oscillating at a frequency proportional to the data rate of the serial data signal minus the frequency of the first clock signal when the frequency of the data rate of the serial data signal is higher than the first clock signal.
18. The reference clock generator device of claim 17 , wherein the first clock signal comprises an in-phase clock signal and a quadrature clock signal, and wherein the beat frequency generator comprises:
a first flip-flop configured to sample the in-phase clock signal on rising edges of the serial data signal to produce an in-phase sample signal;
a second flip-flop configured to sample the quadrature clock signal on rising edges of the serial data signal to produce a quadrature sample signal; and
circuitry configured to generate the fast difference signal and the slow difference signal utilizing the in-phase sample signal and the quadrature sample signal.
19. The reference clock generator device of claim 18 , wherein the circuitry configured to generate the fast difference signal and slow difference signal comprises:
a mobius circuit configured to shift a signal according to the sequence of the in-phase sample signal and the quadrature sample signal; and
circuitry configured to receive signals from the mobius circuit and produce the slow difference signal that pulses when the data rate of the serial data signal is higher than frequency of the first clock signal and the fast difference signal that pulses when than frequency of the first clock signal is higher the data rate of the serial data signal.
20. The reference clock generator device of claim 14 , wherein the frequency comparison indicator comprises:
an up comparison signal that signals that the frequency of the first clock signal is less than the data rate of the serial data signal;
a down comparison signal that signals that the frequency of the first clock signal is greater than the data rate of the serial data signal; and
wherein the oscillator is further configured to increase the frequency of the first clock signal when the up comparison signal is active and the down comparison signal is inactive and to decrease the frequency of the first clock signal when the down comparison signal is active and the up comparison signal is inactive.
21. The reference clock generator device of claim 20 , wherein the frequency difference detector comprises:
a first counter configured to increment on rising edges of the fast difference signal, reset to zero when a reset signal is asserted, and assert an up limit signal when the counter reaches a maximum value;
a second counter configured to increment on rising edges of the slow difference signal, reset to zero when the reset signal is asserted, and assert a down limit signal when the counter reaches the maximum value;
a third counter configured to increment on rising edges of the output signal of the first divider, reset to zero when the reset signal is asserted, and assert a clock limit signal when the counter reaches the maximum value;
logic circuitry configured to assert the reset signal when any of the counters reaches the maximum value; and
circuitry configured to produce the up comparison signal and the down comparison signal utilizing the up limit signal, the down limit signal, and the clock limit signal.
22. The reference clock generator device of claim 21 , wherein the circuitry configured to produce the up comparison signal and the down comparison signal comprises:
a first set-reset latch configured to set when the clock limit signal is asserted, to reset when either the up limit signal or the down reset signal is asserted, and to produce an unlocked signal that is active when the latch is reset and inactive when the latch is set;
a second set-reset latch configured to set when the up reset signal is asserted and reset when the down reset signal is asserted; and
selection circuitry configured to supply, when the unlocked signal is inactive, the up comparison signal and the down comparison signal having the same value and to supply, when the unlocked signal is active, the up comparison signal that is active when the second set-reset latch is set and inactive when the second set-reset latch is reset and the down comparison signal that is active when the second set-reset latch is reset and inactive when the second set-reset latch is set.
23. A method for use in recovering clock and data from a serial input signal, comprising:
generating a variable clock signal oscillating at a frequency;
dividing down the variable clock signal to produce a feedback clock signal oscillating at a lower frequency than the frequency of the variable clock signal;
generating a beat frequency indicator indicating a difference between a data rate of the serial input signal and the frequency of the variable clock signal;
comparing the frequency of the feedback clock signal to the beat frequency indicator to produce a frequency comparison indicator; and
conditionally adjusting the frequency of the variable clock signal based on the frequency comparison indicator, wherein conditionally adjusting the frequency of the variable clock signal comprises adjusting the frequency of the variable clock signal when the frequency comparison indicator indicates that a magnitude of the beat frequency indicator is greater than the frequency of the feedback clock signal.
24. The method of claim 23 , further comprising:
recovering data values from the serial data signal utilizing the variable clock signal as a reference signal.
25. The method of claim 23 , wherein the beat frequency indicator comprises an indicator of a magnitude of the frequency difference between the data rate of the serial input signal and the frequency of the variable clock signal and an indicator of whether the frequency of the variable clock signal is greater than or less than the data rate of the serial input signal.
26. The method of claim 25 , wherein adjusting the frequency of the variable clock signal when the frequency comparison indicator indicates that the magnitude of the beat frequency indicator is greater than the frequency of the feedback clock signal comprises:
increasing the frequency of the variable clock signal when beat frequency indicator indicates that the frequency of the variable clock signal is less than the data rate of the serial input signal; and
decreasing the frequency of the variable clock signal when beat frequency indicator indicates that the frequency of the variable clock signal is greater than the data rate of the serial input signal.