Patent Assignment
Reel/Frame 023234/0037
Release of Security Interest
Recorded: 2009-09-15
Pages: 10
Assignor
COMERICA BANK
Executed: 2009-09-11
Assignee
LOGICVISION, INC.
25 METRO DRIVE, 3RD FLOOR, SAN JOSE, CALIFORNIA, 95110
Covered Properties
(64)
Method and Apparatus for Testing Digital to Analog and Analog to Digital Converters
Patent:
5,659,312 →
Application:
08/663,493 →
Bist Architecture for Measurement of Integrated Circuit Delays
Patent:
5,923,676 →
Application:
08/771,302 →
Asynchronous Interface
Patent:
5,900,753 →
Application:
08/825,446 →
Method and Apparatus for High-Speed Interconnect Testing
Patent:
6,000,051 →
Application:
08/948,842 →
Method for Testability Analysis and Test Point Insertion at the Rt-Level of a Hardware Development Language (Hdl) Specification
Patent:
6,363,520 →
Application:
09/098,555 →
Method and Circuit for Built in Self Test of Phase Locked Loops
Patent:
6,396,889 →
Application:
09/184,516 →
Test Circuit and Method for Measuring Switching Point Voltages and Integral Non-Linearity (Inl) of Analog to Digital Converters
Patent:
6,211,803 →
Application:
09/191,154 →
Method and Apparatus for Scan Testing Digital Circuits
Patent:
6,145,105 →
Application:
09/192,839 →
Clock Skew Management Method and Apparatus
Patent:
6,115,827 →
Application:
09/209,790 →
Method and Apparatus for Controlling Power Level During Bist
Patent:
6,330,681 →
Application:
09/218,764 →
Method of Testing at-Speed Circuits Having Asynchronous Clocks and Controller for Use Therewith
Patent:
6,327,684 →
Application:
09/309,827 →
Programmable Clock Signal Generation Circuits and Methods for Generating Accurate, High Frequency, Clock Signals
Patent:
6,204,694 →
Application:
09/316,197 →
Method and Apparatus for Testing Circuits with Multiple Clocks
Patent:
6,442,722 →
Application:
09/430,686 →
Method for Testing Circuits with Tri-State Drivers and Circuit for Use Therewith
Patent:
6,487,688 →
Application:
09/472,386 →
Method and Circuit for Testing Dc Parameters of Circuit Input and Output Nodes
Patent:
6,586,921 →
Application:
09/570,412 →
Method and Apparatus for Testing High Performance Circuits
Patent:
6,510,534 →
Application:
09/607,128 →
Hierarchical Design and Test Method and System, Program Product Embodying the Method and Integrated Circuit Produced Thereby
Patent:
6,615,392 →
Application:
09/626,877 →
Method for Scan Controlled Sequential Sampling of Analog Signals and Circuit for Use Therewith
Method for Scan Testing of Digital Circuit, Digital Circuit for Use Therewith and Program Product for Incorporating Test Methodology into Circuit Description
Method and Program Product for Detecting Bus Conflict and Floating Bus Conditions in Circuit Designs
Method and Circuit for Testing High Frequency Mixed Signal Circuits with Frequency Signals
Method of Designing Circuit Having Multiple Test Access Ports, Circuit Produced Thereby and Method of Using Same
Circuit and Method for Detecting Transient Voltages on a Dc Power Supply Rail
Method of Testing Embedded Memory Array and Embedded Memory Controller for Use Therewith
Method and system for collecting diverse data types within a manufacturing environment and accessing the diverse data types through a network portal
Application:
09/896,170 →
Publication:
US 2002/0002560
Method,System and Program Product for Testing and/or Diagnosing Circuits Using Embedded Test Controller Access Data
Method and Program Product for Designing Hierarchical Circuit for Quiescent Current Testing and Circuit Produced Thereby
Method and Program Product for Designing Hierarchical Circuit for Quiescent Current Testing
Circuit Synthesis Method Using Technology Parameters Extracting Circuit
Patent:
6,567,971 →
Application:
10/021,810 →
Circuit and method for compensating for non-linear distortion
Application:
10/100,620 →
Publication:
US 2002/0131523
Method and Circuitry for Controlling Clocks of Embedded Blocks During Logic Bist Test Mode
Test Access Circuit and Method of Accessing Embedded Test Controllers in Integrated Circuit Modules
Method for Collecting Failure Information for a Memory Using an Embedded Test Controller
Circuit and Method for Determining the Location of Defect in a Circuit
Method of Masking Corrupt Bits During Signature Analysis and Circuit for Use Therewith
Scan Test Method for Providing Real Time Identification of Failing Test Patterns and Test Bist Controller for Use Therewith
Semiconductor Characterization and Production Information System
Patent:
6,720,194 →
Application:
10/262,737 →
Method and Circuit for Testing High Frequency Mixed Signal Circuits with Low Frequency Signals
Method and Program Product for Completing a Circuit Design Having Embedded Test Structures
Self-Contained Embedded Test Design Envoronment and Environment Setup Utility
Verification of Embedded Test Structures in Circuit Designs
Method and system for licensing intellectual property circuits
Application:
10/357,203 →
Publication:
US 2003/0149669
Circuit and Method for Adding Parametric Test Capability to Digital Boundary Scan
Method of and Program Product for Performing Gate-Level Diagnosis of Failing Vectors
Circuit and Method for Accurately Applying a Voltage to a Node of an Integrated Circuit
Method and Test Circuit for Testing Memory Internal Write Enable
Method and Circuit for Collecting Memory Failure Information
Ceiling Lamp Junction Box/Lamp Rod Folding Installation Structure
Boundary Scan with Strobed Pad Driver Enable
Method for testing parameters of high speed data signals
Application:
10/724,193 →
Publication:
US 2004/0119455
Circuit and Method for Testing High Speed Data Circuits
Method and Circuit for at-Speed Testing of Scan Circuits
Memory Repair Analysis Method and Circuit
Memory Repair Circuit and Method
Processor interface for test access port
Application:
10/892,203 →
Publication:
US 2005/0028059
Circuit and method for low frequency testing of high frequency signal waveforms
Application:
10/895,356 →
Publication:
US 2005/0229053
Circuit and Method for Measuring Jitter of High Speed Signals
Circuit and Method for Measuring Delay of High Speed Signals
Clock Controller for at-Speed Testing of Scan Circuits
Clocking Methodology for at-Speed Testing of Scan Circuits with Synchronous Clocks
Masking circuit and method of masking corrupted bits
Application:
11/109,844 →
Publication:
US 2005/0240848
Insertion of embedded test in RTL to GDSII flow
Application:
11/144,764 →
Publication:
US 2005/0273683
Method for at-Speed Testing of Memory Interface Using Scan
Method and Apparatus for Storing and Distributing Memory Repair Information
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Agreement
May 4, 2009
From: LOGICVISION, INC.
To: COMERICA BANK
Reel/Frame 022629/0938 →
Assignment of Assignor's Interest
Apr 14, 2010
From: LOGICVISION, INC.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 024233/0056 →
Merger and Change of Name
Jun 16, 2021
From: MENTOR GRAPHICS CORPORATION; SIEMENS INDUSTRY SOFTWARE INC.
To: SIEMENS INDUSTRY SOFTWARE INC.
Reel/Frame 057279/0707 →