IP Library Granted Patent US 7,142,596
Granted Patent B2
US 7,142,596 · App. 10/872,307 · Granted Nov 28, 2006

Integrated circuit implementation for power and area efficient adaptive equalization

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,142,596
App. No.
10/872,307
Granted
Nov 28, 2006
Kind
B2
Abstract

Methods, apparatuses, and systems are presented for performing channel equalization involving receiving a signal from a channel associated with inter-s interference (ISI), providing the received signal to an inductor, capacitor, resistance (LCR) network comprising a plurality of inductors and a plurality of capacitors, generating in the LCR network a first plurality of intermediate signals representing voltages associated with capacitors in the LCR network and a second plurality of intermediate signals representing currents associated with inductors in the LCR network, wherein the first plurality and second plurality of intermediate signals correspond to application of linearly independent impulse responses to the received signal, applying a corresponding one of a plurality of multiplier factors to each of the first plurality and second plurality of intermediate signals, and generating from the LCR network a resulting signal corresponding to an equalized version of the received signal.

Claims (70)

1. A method for performing channel equalization comprising:

receiving a signal from a channel associated with inter-symbol interference (ISI);

providing the received signal to an inductor, capacitor, resistance (LCR) network comprising a plurality of inductors and a plurality of capacitors;

generating in the LCR network a first plurality of intermediate signals representing voltages associated with capacitors in the LCR network and a second plurality of intermediate signals representing currents associated with inductors in the LCR network, wherein the first plurality and second plurality of intermediate signals correspond to application of linearly independent impulse responses to the received signal;

applying a corresponding one of a plurality of multiplier factors to each of the first plurality and second plurality of intermediate signals; and

generating from the LCR network a resulting signal corresponding to an equalized version of the received signal.

2. The method of claim 1 wherein the applying step comprises detecting each of the first plurality and second plurality of intermediate signals and scaling each of the first plurality and second plurality of intermediate signals by the corresponding multiplier factor.

3. The method of claim 2 wherein each of the first plurality of intermediate signals is detected in voltage form, converted to current form, and scaled by the corresponding multiplier factor.

4. The method of claim 2 wherein each of the second plurality of intermediate signals is detected in voltage form using a sense resistor placed in series with an associated inductor in the LCR network, converted to current form, and scaled by the corresponding multiplier factor.

5. The method of claim 2 wherein each of the second plurality of intermediate signals is detected in voltage form using a sense inductor placed adjacent to and inductively coupled to an associated inductor in the LCR network, converted to current form, and scaled by the corresponding multiplier factor.

6. The method of claim 2 wherein the first plurality and second plurality of intermediate signals are scaled and combined to form a combined current signal, and the combined current signal is passed through a resistor to produce a voltage corresponding to the resulting signal.

7. The method of claim 1 wherein the applying step comprises driving each of the first plurality and second plurality of intermediate signals according to the corresponding multiplier factor.

8. The method of claim 1 wherein the LCR network comprises a primary network and a dual network, the primary network comprising a plurality of primary inductors and primary capacitors, the dual network comprising a plurality of dual inductors corresponding to the primary capacitors and a plurality of dual capacitors corresponding to the primary inductors.

9. The method of claim 8 wherein each of the first plurality of intermediate signals is obtained as a voltage signal associated with a primary capacitor in the primary network, and wherein each of the second plurality of intermediate signals is obtained as a voltage signal associated with a dual capacitor in the dual network.

10. The method of claim 1 wherein the LCR network is implemented as a differential circuit, wherein each of the first plurality of intermediate signals represents a differential voltage associated with a pair of capacitors, and wherein each of the second plurality of intermediate signals represents current associated with at least one of a pair of inductors.

11. The method of claim 10 wherein the pair of inductors are inductively coupled to one another.

12. The method of claim 11 wherein currents in the pair of inductors flow in opposite directions.

13. The method of claim 11 wherein the pair of inductors are inter-wound such that magnetic fields of the inductors reinforce one another.

14. The method of claim 1 wherein the LCR network is a passive network.

15. The method of claim 1 wherein the LCR network represents a Bessel filter having a bandwidth within an order of magnitude as a data transmission rate associated with the received signal.

16. The method of claim 1 further comprising a step of dynamically adjusting the multiplier factors to reduce an error measure based on the resulting signal.

17. The method of claim 16 wherein the multiplier factors are dynamically adjusted according to a least mean square (LMS) algorithm utilizing the first plurality and second plurality of intermediate signals as gradient signals.

18. The method of claim 1 wherein the corresponding multiplier factor is applied to each of the first plurality and second plurality of intermediate signals using a range-switched transconductor, the range-switched transconductor comprising a plurality of transconductor elements, each element capable of contributing to an output of the range-switched transconductor by generating an elemental output according to a different range of the corresponding multiplier factor.

19. A method for performing channel equalization comprising:

receiving a signal from a channel associated with inter-symbol interference (ISI);

applying a plurality of multiplier factors to the received signal to generate a plurality of weighted input signals;

providing the weighted input signals to different nodes of an inductor, capacitor, resistance (LCR) network comprising a plurality of inductors and a plurality of capacitors;

in response to the weighted input signals, generating in the LCR network a first plurality of intermediate signals representing voltages associated with capacitors in the LCR network and a second plurality of intermediate signals representing currents associated with inductors in the LCR network; and

generating from the LCR network a resulting signal corresponding to an equalized version of the received signal.

20. The method of claim 19 wherein the LCR network comprises a primary network and a dual network, the primary network comprising a plurality of primary inductors and primary capacitors, the dual network comprising a plurality of dual inductors corresponding to the primary capacitors and a plurality of dual capacitors corresponding to the primary inductors.

21. The method of claim 20 wherein each of the first plurality of intermediate signals is obtained as a voltage signal associated with a primary capacitor in the primary network, and wherein each of the second plurality of intermediate signals is obtained as a voltage signal associated with a dual capacitor in the dual network.

22. The method of claim 19 wherein the LCR network is implemented as a differential circuit, wherein each of the first plurality of intermediate signals represents a differential voltage associated with a pair of capacitors, and wherein each of the second plurality of intermediate signals represents current associated with at least one of a pair of inductors.

23. The method of claim 19 wherein the plurality of multiplier factors are applied to the received signal using a plurality of range-switched transconductors, each range-switched transconductor comprising a plurality of transconductor elements, each element capable of contributing to an output of the range-switched transconductor by generating an elemental output according to a different range of the corresponding multiplier factor.

24. An apparatus for performing channel equalization comprising:

an inductor, capacitor, resistance (LCR) network, comprising a plurality of inductors and a plurality of capacitors, capable of receiving a signal from a channel associated with inter-symbol interference (ISI) and generating a first plurality of intermediate signals representing voltages associated with capacitors in the LCR network and a second plurality of intermediate signals representing currents associated with inductors in the LCR network, wherein the first plurality and second plurality of intermediate signals correspond to application of linearly independent impulse responses to the received signal;

a plurality of scaling elements configured to apply a corresponding one of a plurality of multiplier factors to each of the first plurality and second plurality of intermediate signals; and

wherein the LCR network is configured to generate a resulting signal corresponding to an equalized version of the received signal.

25. The apparatus of claim 24 wherein the scaling elements are configured to detect each of the first plurality and second plurality of intermediate signals and scale each of the first plurality and second plurality of intermediate signals by the corresponding multiplier factor.

26. The apparatus of claim 25 further comprising a plurality of transconductors coupled to the LCR network, wherein each of the first plurality of intermediate signals is detected in voltage form, converted to current form, and scaled by a multiplier factor using one of the plurality of transconductors.

27. The apparatus of claim 25 further comprising a plurality of transconductors coupled to the LCR network, wherein each of the second plurality of intermediate signals is detected in voltage form using a sense resistor placed in series with an associated inductor in the LCR network, converted to current form, and scaled by a multiplier factor using one of the plurality of transconductors.

28. The apparatus of claim 25 further comprising a plurality of transconductors coupled to the LCR network, wherein each of the second plurality of intermediate signals is detected in voltage form using an associated sense inductor placed adjacent to and inductively coupled to a corresponding inductor in the LCR network, converted to current form, and scaled by a multiplier factor using the corresponding transconductor.

29. The apparatus of claim 25 wherein the first plurality and second plurality of intermediate signals are scaled and combined to form a combined current signal, and the combined current signal is passed through a resistor to produce a voltage corresponding to the resulting signal.

30. The apparatus of claim 24 wherein the scaling elements are configured to drive each of the first plurality and second plurality of intermediate signals according to the corresponding multiplier factor.

31. The apparatus of claim 24 wherein the LCR network comprises a primary network and a dual network, the primary network comprising a plurality of primary inductors and primary capacitors, the dual network comprising a plurality of dual inductors corresponding to the primary capacitors and a plurality of dual capacitors corresponding to the primary inductors.

32. The apparatus of claim 24 wherein each of the first plurality of intermediate signals is obtained as a voltage signal associated with a primary capacitor in the primary network, and wherein each of the second plurality of intermediate signals is obtained as a voltage signal associated with a dual capacitor in the dual network.

33. The apparatus of claim 24 wherein the LCR network is implemented as a differential circuit, wherein each of the first plurality of intermediate signals represents a differential voltage associated with a pair of capacitors, and wherein each of the second plurality of intermediate signals represents current associated with at least one of a pair of inductors.

34. The apparatus of claim 33 wherein the pair of inductors are inductively coupled to one another.

35. The apparatus of claim 34 wherein the pair of inductors allow currents to flow in opposite directions.

36. The apparatus of claim 34 wherein the pair of inductors are inter wound such that magnetic fields of the inductors reinforce one another.

37. The apparatus of claim 24 wherein the LCR network is a passive network.

38. The apparatus of claim 24 wherein the LCR network represents a Bessel filter having a bandwidth within an order of magnitude as a data transmission rate associated with the received signal.

39. The apparatus of claim 24 further comprising an adaptation module for dynamically adjusting the multiplier factors to reduce an error measure based on the resulting signal.

40. The apparatus of claim 39 wherein the multiplier factors are dynamically adjusted according to a least mean square (LMS) algorithm utilizing the first plurality and second plurality of intermediate signals as gradient signals.

41. The apparatus of claim 31 further comprising at least one range-switched transconductor coupled to the LCR network and capable of scaling each of the first plurality and second plurality of intermediate signals according to the corresponding multiplier factor, the range-switched transconductor comprising a plurality of transconductor elements, each element capable of contributing to an output of the range-switched transconductor by generating an elemental output according to a different range of the corresponding multiplier factor.

42. An apparatus for performing channel equalization comprising:

an inductor, capacitor, resistance (LCR) network, comprising a plurality of inductors and a plurality of capacitors, capable of operating in response to a signal received from a channel associated with inter-symbol interference (IS I);

a plurality of scaling elements configured to apply a corresponding one of a plurality of multiplier factors to the received signal to generate a plurality of weighted input signals;

wherein the LCR network includes different nodes configured to receiving the plurality of weighted input signals; and

wherein the LCR network is capable of generating a first plurality of intermediate signals representing voltages associated with capacitors in the LCR network and a second plurality of intermediate signals representing currents associated with inductors in the LCR network, in response to the weighted input signals; and

wherein the LCR network is configured to generate a resulting signal corresponding to an equalized version of the received signal.

43. The apparatus of claim 42 wherein the LCR network comprises a primary network and a dual network, the primary network comprising a plurality of primary inductors and primary capacitors, the dual network comprising a plurality of dual inductors corresponding to the primary capacitors and a plurality of dual capacitors corresponding to the primary inductors.

44. The apparatus of claim 43 wherein each of the first plurality of intermediate signals is obtained as a voltage signal associated with a primary capacitor in the primary network, and wherein each of the second plurality of intermediate signals is obtained as a voltage signal associated with a dual capacitor in the dual network.

45. The apparatus of claim 42 wherein the LCR network is implemented as a differential circuit, wherein each of the first plurality of intermediate signals represents a differential voltage associated with a pair of capacitors, and wherein each of the second plurality of intermediate signals represents current associated with at least one of a pair of inductors.

46. The apparatus of claim 42 wherein the plurality of multiplier factors are applied to the received signal using a plurality of range-switched transconductors, each range-switched transconductor comprising a plurality of transconductor elements, each element capable of contributing to an output of the range-switched transconductor by generating an elemental output according to a different range of the corresponding multiplier factor.

47. A system for performing channel equalization comprising:

means for receiving a signal from a channel associated with inter symbol interference (ISI);

means for providing the received signal to an inductor, capacitor, resistance (LCR) network comprising a plurality of inductors and a plurality of capacitors;

means for generating in the LCR network a first plurality of intermediate signals representing voltages associated with capacitors in the LCR network and a second plurality of intermediate signals representing currents associated with inductors in the LCR network, wherein the first plurality and second plurality of intermediate signals correspond to application of linearly independent impulse responses to the received signal;

means for applying a corresponding one of a plurality of multiplier factors to each of the first plurality and second plurality of intermediate signals; and

means for generating from the LCR network a resulting signal corresponding to an equalized version of the received signal.

Assignments (20)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.), INC.; MICROSEMI FREQUENCY AND TIME CORPORATION; MICROSEMI COMMUNICATIONS, INC.; MICROSEMI SOC CORP.; MICROSEMI CORP. - POWER PRODUCTS GROUP; MICROSEMI CORP. - RF INTEGRATED SOLUTIONS
Reel/Frame 046251/0391 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2017
From: MICROSEMI COMMUNICATIONS, INC.
To: MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 042523/0577 →
PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC. (F/K/A LEGERITY, INC., ZARLINK SEMICONDUCTOR (V.N.) INC., CENTELLAX, INC., AND ZARLINK SEMICONDUCTOR (U.S.) INC.); MICROSEMI FREQUENCY AND TIME CORPORATION (F/K/A SYMMETRICON, INC.); MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION); MICROSEMI SOC CORP. (F/K/A ACTEL CORPORATION); MICROSEMI CORP. - POWER PRODUCTS GROUP (F/K/A ADVANCED POWER TECHNOLOGY INC.); MICROSEMI CORP. - RF INTEGRATED SOLUTIONS (F/K/A AML COMMUNICATIONS, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037691/0697 →
RELEASE OF SECURITY INTEREST Recorded Jan 19, 2016
From: BANK OF AMERICA, N.A.
To: MICROSEMI CORPORATION; MICROSEMI CORP.-ANALOG MIXED SIGNAL GROUP, A DELAWARE CORPORATION; MICROSEMI SOC CORP., A CALIFORNIA CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC., A DELAWARE CORPORATION; MICROSEMI FREQUENCY AND TIME CORPORATION, A DELAWARE CORPORATION; MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION), A DELAWARE CORPORATION; MICROSEMI CORP.-MEMORY AND STORAGE SOLUTIONS (F/K/A WHITE ELECTRONIC DESIGNS CORPORATION), AN INDIANA CORPORATION
Reel/Frame 037558/0711 →
MERGER AND CHANGE OF NAME Recorded May 13, 2015
From: VITESSE SEMICONDUCTOR CORPORATION; LLIU100 ACQUISITION CORP.
To: MICROSEMI COMMUNICATIONS, INC.
Reel/Frame 035651/0708 →
SUPPLEMENTAL SECURITY AGREEMENT Recorded Apr 29, 2015
From: MICROSEMI COMMUNICATIONS, INC.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 035532/0925 →
RELEASE OF SECURITY INTEREST Recorded Apr 28, 2015
From: WHITEBOX VSC, LTD.
To: VITESSE SEMICONDUCTOR CORPORATION
Reel/Frame 035526/0090 →
RELEASE OF SECURITY INTEREST Recorded Nov 5, 2014
From: US BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: VITESSE SEMICONDUCTOR CORPORATION
Reel/Frame 034176/0162 →