IP Library › Granted Patent US 12,243,955
Granted Patent B2
US 12,243,955 · App. 16/399,853 · Granted Mar 4, 2025

Display and micro device array for transfer to a display substrate

Inventors: Andreas Bibl (Los Altos, CA); John A. Higginson (Santa Clara, CA); Hung-Fai Stephen Law (Los Altos, CA); Hsin-Hua Hu (Los Altos, CA)
Assignee: Apple Inc.
H01L33/06F21V7/00H01L27/15H01L29/0684H01L33/0093H01L33/04H01L33/28H01L33/30H01L25/0753H01L33/20H01L2224/95
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Quick Facts
Patent No.
US 12,243,955
App. No.
16/399,853
Granted
Mar 4, 2025
Kind
B2
Abstract

A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.

Claims (24)

1. A structure comprising:

a substrate layer;

an array of posts protruding from the substrate layer;

a continuous bonding layer comprising a metal or metal alloy on the array of posts and the substrate; and

a corresponding array of laterally separate micro devices on the bonding layer on top of the array of posts, wherein each micro device includes a bottom surface that is wider than a corresponding post top surface directly underneath the micro device.

2. The structure of claim 1 , wherein the array of posts and the substrate layer are a single piece of material.

3. The structure of claim 2 , wherein the single piece of material comprises a polymer material.

4. The structure of claim 2 , wherein each of the micro devices is of 1-100 μm scale.

5. The structure of claim 2 , wherein each micro device includes a micro p-n diode layer comprising:

a p-doped layer;

an n-doped layer; and

a quantum well layer between the p-doped layer and the n-doped layer.

6. The structure of claim 5 , wherein each micro device includes a metallization layer between a micro p-n diode layer and a corresponding post.

7. The structure of claim 5 , wherein each of the posts has a height of 0.2-4 μm.

8. The structure of claim 5 , further comprising a dielectric layer spanning the bottom surface of each micro device, side surfaces of each post, and over the bonding layer laterally between adjacent posts.

9. The structure of claim 5 , wherein each micro device includes a metallization layer between a micro p-n diode layer and a corresponding post, and each metallization layer includes a bottom surface that is wider than the corresponding post top surface directly underneath the micro device.

10. The structure of claim 9 , wherein the bottom surface of each micro device is wider than a top surface of each corresponding metallization layer.

11. The structure of claim 9 , wherein each metallization layer makes ohmic contact with each corresponding micro device.

12. The structure of claim 9 , wherein each metallization layer is reflective to light emission.

13. The structure of claim 9 , wherein the p-doped layer has a thickness of approximately 0.1-1 μm.

14. The structure of claim 9 , wherein the n-doped layer has a thickness of approximately 0.1-6 μm.

15. The structure of claim 9 , wherein the micro p-n diode layer has a thickness of less than approximately 9.3 μm.

16. The structure of claim 9 , wherein each micro p-n diode layer comprises a top surface, a bottom surface, and tapered sidewalls.

17. The structure of claim 16 , wherein the top surface of the micro p-n diode layer is wider than the bottom surface of the micro p-n diode layer.

Continuity (5)
Continuation 14312554 · Jun 23, 2014
Continuation 13372258 · Feb 13, 2012
Provisional Application 61594919 · Feb 3, 2012
Provisional Application 61561706 · Nov 18, 2011
Related Publication 20190259907A1 · Aug 22, 2019
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US 12,593,556