IP Library Granted Patent US 12,243,776
Granted Patent B2
US 12,243,776 · App. 17/508,036 · Granted Mar 4, 2025

Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings

Inventors: Roshan Jayakhar Tirukkonda (Milpitas, CA); Senaka Kanakamedala (San Jose, CA); Raghuveer S. Makala (Campbell, CA); Rahul Sharangpani (Fremont, CA); Monica Titus (Santa Clara, CA); Adarsh Rajashekhar (Santa Clara, CA)
Assignee: Sandisk Technologies, Inc.
H01L21/7688H01L21/30608H01L21/3081H01L21/76811
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Quick Facts
Patent No.
US 12,243,776
App. No.
17/508,036
Granted
Mar 4, 2025
Kind
B2
Abstract

A source-level semiconductor layer and an alternating stack of first material layers and second material layers is formed above a substrate. A hard mask layer is formed over the alternating stack, and is subsequently patterned to provide a pattern of cavities therethrough. Via openings are formed through the alternating stack by performing an anisotropic etch process. A cladding liner is formed on sidewalls of the cavities in the hard mask layer and on a top surface of the hard mask layer. The via openings are vertically extended at least through the source-level semiconductor layer by performing a second anisotropic etch process employing a combination of the cladding liner and the hard mask layer as an etch mask.

Claims (38)

1. A method of forming a semiconductor structure, comprising:

forming a source-level semiconductor layer over a substrate;

forming an alternating stack of first material layers and second material layers over the source-level semiconductor layer;

forming a hard mask layer over the alternating stack;

forming cavities in the hard mask layer;

forming via openings through the alternating stack by performing an anisotropic etch process that transfers a pattern of the cavities in the hard mask layer through the alternating stack;

forming a cladding liner on sidewalls of the cavities in the hard mask layer and on a top surface of the hard mask layer; and

vertically extending the via openings at least through the source-level semiconductor layer by performing an additional anisotropic etch process employing a combination of the cladding liner and the hard mask layer as an etch mask.

2. The method of claim 1 , wherein the cladding liner is formed by depositing an aluminum oxide material.

3. The method of claim 2 , wherein:

the aluminum oxide material that is deposited to form the cladding liner comprises an amorphous aluminum oxide material; and

the method further comprises converting at least an upper portion of the amorphous aluminum oxide material into a polycrystalline aluminum oxide material portion prior to performing the additional anisotropic etch process.

4. The method of claim 3 , wherein:

the upper portion of the amorphous aluminum oxide material comprises a horizontally-extending portion of the amorphous aluminum oxide material located above a horizontal plane including a top surface of the hard mask layer; and

the upper portion of the amorphous aluminum oxide material further comprises a plurality of tubular portions of the amorphous aluminum oxide material that are in contact with upper segments of cylindrical sidewalls of the cavities in the hard mask layer.

5. The method of claim 3 , further comprising selectively etching remaining amorphous aluminum oxide lower portions of the cladding liner selective to polycrystalline aluminum oxide material portion and selective to the alternating stack prior to performing the additional anisotropic etch process.

6. The method of claim 1 , wherein:

the hard mask layer comprises a carbon hard mask layer; and

the method further comprises ashing the carbon hard mask layer and lifting off the polycrystalline aluminum oxide material portion during the ashing.

7. The method of claim 1 , wherein the cladding liner is formed by conformally depositing an amorphous aluminum oxide material on sidewalls of the alternating stack around the via openings, on sidewalls of the cavities in the hard mask layer, and on a top surface of the hard mask layer.

8. The method of claim 7 , further comprising converting an upper portion of the amorphous aluminum oxide material in contact with a top surface of the hard mask layer into a polycrystalline aluminum oxide material portion while lower portions of the amorphous aluminum oxide material in contact with the sidewalls of the alternating stack around the via openings remain amorphous.

9. The method of claim 8 , wherein the converting the upper portion of the amorphous aluminum oxide material in contact with the top surface of the hard mask layer into the polycrystalline aluminum oxide material portion comprises performing a laser anneal process that selectively irradiates a horizontally-extending portion of the amorphous aluminum oxide material located on the top surface of the hard mask layer without irradiating the lower portions of the amorphous aluminum oxide material in contact with the sidewalls of the alternating stack around the via openings.

10. The method of claim 9 , wherein an angle of incidence of a laser beam that impinges on the horizontally-extending portion of the amorphous aluminum oxide material located on the top surface of the hard mask layer is in a range from 60 degrees to 89.9 degrees with respect to a vertical direction that is perpendicular to the top surface of the hard mask layer.

11. The method of claim 8 , further comprising selectively etching the lower portions of the amorphous aluminum oxide material selective to the polycrystalline aluminum oxide material portion and selective to the alternating stack prior to performing the additional anisotropic etch process.

12. The method of claim 1 , wherein the cladding liner is formed by non-conformally depositing an amorphous aluminum oxide material on a top surface of the hard mask layer and on sidewalls of the cavities in the hard mask layer.

13. The method of claim 12 , further comprising converting an upper portion of the amorphous aluminum oxide material in contact with a top surface of the hard mask layer into a polycrystalline aluminum oxide material portion while lower portions of the amorphous aluminum oxide material in contact with lower segments of the sidewalls of the cavities in the hard mask layer remain amorphous.

14. The method of claim 13 , wherein the converting the portion of the amorphous aluminum oxide material in contact with the top surface of the hard mask layer into the polycrystalline aluminum oxide material portion comprises performing a laser anneal process that selectively irradiates a horizontally-extending portion of the amorphous aluminum oxide material located on the top surface of the hard mask layer without irradiating the portions of the amorphous aluminum oxide material in contact with the lower segments of the sidewalls of the cavities in the hard mask layer.

15. The method of claim 13 , further comprising selectively etching the lower portions of the amorphous aluminum oxide material selective to the polycrystalline aluminum oxide material portion and selective to the alternating stack prior to performing the additional anisotropic etch process.

16. The method of claim 12 , further comprising converting an entirety of the amorphous aluminum oxide material into a polycrystalline aluminum oxide material layer.

17. The method of claim 16 , wherein converting the entirety of the amorphous aluminum oxide material into the polycrystalline aluminum oxide material layer comprises performing a rapid thermal anneal process in which the alternating stack, the hard mask layer, and the amorphous aluminum oxide material are annealed at an elevated temperature at which the amorphous aluminum oxide material is converted into the polycrystalline aluminum oxide material layer.

18. The method of claim 1 , wherein the forming a source-level semiconductor layer comprises:

forming an additional source-level semiconductor layer located underneath a source-level sacrificial layer;

vertically extending the via openings through the source-level sacrificial layer and into an upper portion of the additional source-level semiconductor layer during the additional anisotropic etch process; and

replacing the source-level sacrificial layer with a source contact layer after the additional anisotropic etch process.

19. The method of claim 1 , further comprising removing the hard mask layer after the additional anisotropic etch process.

20. The method of claim 19 , further comprising:

forming memory opening fill structures in the via openings after removing the hard mask layer, wherein each of the memory opening fill structures comprises a respective vertical semiconductor channel and a respective vertical stack of memory elements; and

replacing the second material layers with electrically conductive layers after formation of the memory opening fill structures.

Assignments (8)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 2ND APPLICATION NUMBER SHOULD BE DELETED PREVIOUSLY RECORDED AT REEL: 064275 FRAME: 0442. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 28, 2023
From: TIRUKKONDA, ROSHAN JAYAKHAR; SONDHI, KARTIK; MAKALA, RAGHUVEER S.; KANAKAMEDALA, SENAKA
To: INC., WESTERN DIGITAL TECHNOLOGIES
Reel/Frame 066141/0473 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 9TH APPLICATION NUMBER SHOULD BE DELETED PREVIOUSLY RECORDED AT REEL: 064275 FRAME: 0472. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 28, 2023
From: SHARANGPANI, RAHUL; KANAKAMEDALA, SENAKA; MAKALA, RAGHUVEER S.; TIRUKKONDA, ROSHAN J.; SONDHI, KARTIK
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 066141/0921 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2023
From: SHARANGPANI, RAHUL; KANAKAMEDALA, SENAKA; MAKALA, RAGHUVEER S.; TIRUKKONDA, ROSHAN JAYAKHAR; SONDHI, KARTIK
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 064275/0472 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2023
From: TIRUKKONDA, ROSHAN JAYAKHAR; SONDHI, KARTIK; MAKALA, RAGHUVEER S.; KANAKAMEDALA, SENAKA
To: WESTERN DIGITAL TECHNOLOGIES, INC.,
Reel/Frame 064275/0442 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2021
From: TIRUKKONDA, ROSHAN JAYAKHAR; KANAKAMEDALA, SENAKA; MAKALA, RAGHUVEER S; SHARANGPANI, RAHUL; TITUS, MONICA; RAJASHEKHAR, ADARSH
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 057875/0697 →
Continuity (4)
Continuation In Part 17494114 · Oct 5, 2021
Continuation In Part 17355955 · Jun 23, 2021
Continuation In Part 17136471 · Dec 29, 2020
Related Publication 20220208600A1 · Jun 30, 2022
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