Package architecture with vertical stacking of integrated circuit dies having planarized edges and multi-side routing
Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface; a second region attached to the first region along a first planar interface that is orthogonal to the first surface; and a third region attached to the second region along a second planar interface that is parallel to the first planar interface, the third region having a second surface, the second surface being coplanar with the first surface. The first region and the third region comprise a plurality of layers of conductive traces in a dielectric material, the conductive traces being orthogonal to the first and second surfaces; and bond-pads on the first and second surfaces, the bond-pads comprising portions of the respective conductive traces exposed on the first and second surfaces.
1 . An integrated circuit (IC) die, comprising:
a first region having a first surface and a second surface, the first surface being orthogonal to the second surface;
a second region attached to the first region along a first planar interface that is orthogonal to the first surface and parallel to the second surface, the second region having a third surface coplanar with the first surface; and
a third region attached to the second region along a second planar interface that is parallel to the first planar interface, the third region having a fourth surface, the fourth surface being coplanar with the first surface and the third surface;
wherein:
the first region and the third region comprise:
a dielectric material;
a plurality of layers of conductive traces in the dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface;
conductive vias through the dielectric material, the conductive vias being orthogonal to the conductive traces; and
bond-pads on the first surface and the fourth surface, the bond-pads comprising portions of respective conductive traces exposed on the first surface and the fourth surface, and
the second region comprises a material different from the dielectric material.
2 . The IC die of claim 1 , further comprising a through-substrate via (TSV) in the second region.
3 . The IC die of claim 2 , wherein the TSV conductively couples the first plurality of conductive traces and the second plurality of conductive traces.
4 . The IC die of claim 1 , wherein:
the plurality of conductive traces in the first region comprises a first plurality of conductive traces,
the plurality of conductive traces in the second region comprises a second plurality of conductive traces, and
at least one conductive trace in the first plurality of conductive traces is thinner than at least another conductive trace in the second plurality of conductive traces.
5 . The IC die of claim 1 , wherein the second region comprises active circuitry proximate to the first planar interface.
6 . The IC die of claim 1 , wherein the first surface is flat and planar with surface roughness less than 10 Angstroms and total thickness variation (TTV) across the first surface of less than 3 micrometers.
7 . The IC die of claim 1 , wherein the second region comprises active circuitry proximate to the second planar interface.
8 . A microelectronic assembly, comprising:
a first IC die coupled to a second IC die by interconnects on a first surface of the first IC die and a second surface of the second IC die such that the first surface is in contact with the second surface,
wherein:
the interconnects comprise dielectric-dielectric bonds and metal-metal bonds,
the metal-metal bonds include first bond-pads in the first IC die and second bond-pads in the second IC die,
the first IC die comprises a substrate between metallization stacks,
the metallization stacks are attached to the substrate on opposing planar interf 1 aces, the planar interfaces are orthogonal to the first surface,
the metallization stacks comprise respective pluralities of layers of conductive traces in a dielectric material, and
the first bond-pads comprise portions of the conductive traces exposed on the first surface.
9 . The microelectronic assembly of claim 8 , further comprising:
another dielectric material around the first IC die, the another dielectric material in contact with the second surface of the second IC die.
10 . The microelectronic assembly of claim 9 , wherein the another dielectric material comprises an organic polymer with thermally conductive fillers.
11 . The microelectronic assembly of claim 8 , wherein:
the substrate of the first IC die is a first substrate, the metallization stacks of the first IC die are first metallization stacks, and the dielectric material is a first dielectric material,
the second IC die comprises a second metallization stack and a second substrate,
the second substrate is attached to the second metallization stack along another planar interface that is parallel to the second surface, and
the second metallization stack comprises conductive traces in a second dielectric material, the conductive traces coupled by conductive vias to the second bond-pads.
12 . The microelectronic assembly of claim 8 , further comprising a plurality of the first IC dies coupled to the second IC die along respective first surfaces of the first IC dies, wherein:
each first IC die comprises a respective substrate attached to respective metallization stacks along respective planar interfaces on either side of the substrate, and
the respective planar interfaces are orthogonal to the respective first surface.
13 . The microelectronic assembly of claim 12 , wherein the first IC dies in the plurality of the first IC dies are mutually parallel and spaced apart from each other.
14 . The microelectronic assembly of claim 13 , further comprising another dielectric material encapsulating the plurality of the first IC dies, wherein the another dielectric material is in spaces between adjacent ones of the first IC dies.
15 . The microelectronic assembly of claim 12 , wherein the plurality of the first IC dies is arranged in an array of rows and columns.
16 . The microelectronic assembly of claim 12 , wherein the first IC dies are conductively coupled by conductive pathways in the second IC die.
17 . The microelectronic assembly of claim 8 , wherein:
the planar interfaces are first planar interfaces,
the interconnects are first interconnects,
the first IC die has a third surface opposite to the first surface,
the microelectronic assembly further comprises:
a third IC die parallel to the second IC die, the third IC die having a fourth surface and a fifth surface, the fifth surface being opposite to the fourth surface, the fourth surface being coupled to the third surface of the first IC die by second interconnects; and
a fourth IC die parallel to the first IC die, the fourth IC die having a sixth surface, the sixth surface being coupled to the fifth surface of the third IC die by third interconnects,
the second IC die comprises a respective substrate attached to a respective metallization stack along a second planar interface orthogonal to the first planar interfaces,
the third IC die comprises a respective substrate attached to a respective metallization stack along a third planar interface orthogonal to the first planar interfaces, and
the fourth IC die comprises a respective substrate attached to respective metallization stacks on either side of the substrate along fourth planar interfaces parallel to the first planar interfaces.
18 . The microelectronic assembly of claim 17 , further comprising another dielectric material around the first IC die and the fourth IC die.
19 . A microelectronic assembly, comprising:
a first IC die coupled to a second IC die by interconnects on a first surface of the first IC die and a second surface of the second IC die such that the first surface is in contact with the second surface,
wherein:
the interconnects comprise dielectric-dielectric bonds and metal-metal bonds,
the metal-metal bonds include first bond-pads in the first IC die and second bond-pads in the second IC die,
the first IC die comprises a substrate between metallization stacks,
the metallization stacks are attached to the substrate on opposing planar interfaces,
the planar interfaces are orthogonal to the first surface,
the metallization stacks comprise respective pluralities of layers of conductive traces in a dielectric material,
the first bond-pads comprise portions of the conductive traces exposed on the first surface,
the plurality of conductive traces in one of the metallization stacks comprises a first plurality of conductive traces,
the plurality of conductive traces in an other one of the metallization stacks comprises a second plurality of conductive traces, and
at least one conductive trace in the first plurality of conductive traces is thinner than at least another conductive trace in the second plurality of conductive traces.