Device, method, and system to mitigate warpage of a composite chiplet
Techniques and mechanisms to mitigate warping of a composite chiplet. In an embodiment, multiple via structures each extend through an insulator material in one of multiple levels of a composite chiplet. The insulator material extends around an integrated circuit (IC) component in the level. For a given one of the multiple via structures, a respective annular structure extends around the via structure to mitigate a compressive (or tensile) stress due to expansion (or contraction) of the via structure. In another embodiment, the composite chiplet additionally or alternatively comprises a structural support layer on the multiple levels, wherein the structural support layer has formed therein or thereon dummy via structures or a warpage compensation film.
1 . A composite chiplet comprising:
a first integrated circuit (IC) component at a first level;
a second IC component at a second level;
a first layer of a first insulator material at the first level, wherein the first layer extends around the first IC component;
a first conductive via which extends through the first layer and is electrically coupled to circuitry at the second level; and
a first annular structure which extends through the first layer and which surrounds the first conductive via in the first layer, wherein:
a cavity region is in the first annular structure; or
the first annular structure comprises a second material, wherein a first modulus of elasticity of the first insulator material is greater than a second modulus of elasticity of the second material; and
wherein:
a contiguous body of the first insulator material of the first layer forms an entirety of a periphery of the first annular structure at the first level; and
the first conductive via is an only conductive via to extend through the first annular structure.
2 . The composite chiplet of claim 1 , wherein:
the first conductive via is one of multiple conductive vias which extend through the first layer;
the first annular structure is one of multiple annular structures which each extend through the first layer and which each surround a respective one of the multiple conductive vias in the first layer; and
for each one of the multiple annular structures:
a respective cavity region is in the annular structure; or
the annular structure comprises the second material.
3 . The composite chiplet of claim 2 , wherein each of the multiple annular structures surrounds only a respective one of the multiple conductive vias.
4 . The composite chiplet of claim 1 , wherein the first annular structure comprises the second material, and wherein the second material comprises a polymer.
5 . The composite chiplet of claim 1 , wherein the first annular structure comprises the second material, and wherein the second material comprises a low-k porous dielectric.
6 . The composite chiplet of claim 1 , wherein the first annular structure comprises the second material, and wherein the second modulus of elasticity is in a range of 0.1 GigaPascals (GPa) to 10 GPa.
7 . The composite chiplet of claim 1 , further comprising a structural support layer over the second level, wherein multiple dummy vias extend through the structural support layer.
8 . The composite chiplet of claim 7 , further comprising a film on a top surface of the structural support layer, wherein a third modulus of elasticity of the structural support layer is less than a fourth modulus of elasticity of the film.
9 . A system comprising:
a microprocessor; and
a memory coupled to the microprocessor, wherein at least one of the memory or the microprocessor comprises circuitry on a composite chiplet comprising:
a first integrated circuit (IC) component at a first level;
a second IC component at a second level;
a first layer of a first insulator material at the first level, wherein the first layer extends around the first IC component;
a first conductive via which extends through the first layer and is electrically coupled to circuitry at the second level; and
a first annular structure which extends through the first layer and which surrounds the first conductive via in the first layer, wherein:
a cavity region is in the first annular structure; or
the first annular structure comprises a second material, wherein a first modulus of elasticity of the first insulator material is greater than a second modulus of elasticity of the second material; and
wherein:
a contiguous body of the first insulator material of the first layer forms an entirety of a periphery of the first annular structure at the first level; and
the first conductive via is an only conductive via to extend through the first annular structure.
10 . The system of claim 9 , wherein:
the first conductive via is one of multiple conductive vias which extend through the first layer;
the first annular structure is one of multiple annular structures which each extend through the first layer and which each surround a respective one of the multiple conductive vias in the first layer; and
for each one of the multiple annular structures:
a respective cavity region is in the annular structure; or
the annular structure comprises the second material.
11 . The system of claim 9 , wherein the first annular structure comprises the second material, and wherein the second material comprises a polymer.
12 . The system of claim 9 , wherein the first annular structure comprises the second material, and wherein the second material comprises a low-k porous dielectric.
13 . The system of claim 9 , wherein the composite chiplet further comprises a structural support layer over the second level, wherein multiple dummy vias extend through the structural support layer.
14 . The system of claim 13 , wherein the composite chiplet further comprises a film on a top surface of the structural support layer, wherein a third modulus of elasticity of the structural support layer is less than a fourth modulus of elasticity of the film.