Granted Patent B2

US 12,199,106 · App. 18/197,785 · Granted Jan 14, 2025

Inventors: Kouhei Toyotaka (Kanagawa, JP); Jun Koyama (Kanagawa, JP); Hiroyuki Miyake (Kanagawa, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

H01L27/124G02F1/1334G02F1/1337G02F1/134336G02F1/136286G02F1/1368G09G3/20G09G3/3233G09G3/3258G09G3/3648G11C19/28G11C19/287H01L27/1225H01L29/7869G02F2201/121G02F2201/123G09G3/3266G09G3/3275G09G3/3677G09G3/3688G09G2300/0426G09G2310/0286G09G2310/08G09G2320/0626G09G2330/021

Abstract

Claims (35)

1. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor; and

a fourth transistor,

wherein one of a source and a drain of the first transistor and one of a source and a drain of the second transistor are electrically connected to a first wiring,

wherein one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor are electrically connected to a second wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to a third wiring,

wherein the other of the source and the drain of the second transistor is electrically connected to a fourth wiring,

wherein the other of the source and the drain of the third transistor is electrically connected to a fifth wiring,

wherein the other of the source and the drain of the fourth transistor is electrically connected to a sixth wiring,

wherein the first wiring is configured to output a first output signal,

wherein the second wiring is configured to output a second output signal,

wherein the third wiring is configured to be supplied with a first power supply potential,

wherein the fourth wiring is configured to be supplied with a first clock signal,

wherein the fifth wiring is configured to be supplied with a second power supply potential,

wherein the sixth wiring is configured to be supplied with a second clock signal,

wherein the first power supply potential is different from the second power supply potential,

wherein the first clock signal has a first potential and a second potential higher potential than the first potential,

wherein the second clock signal has a third potential and a fourth potential higher than the third potential,

wherein the first potential is higher than the third potential, and

wherein the second potential is higher than the fourth potential.

2. The semiconductor device according to claim 1 ,

wherein the first transistor, the second transistor, the third transistor, and the fourth transistor have the same conductivity type.

3. The semiconductor device according to claim 1 ,

wherein a gate of the first transistor is electrically connected to a gate of the third transistor, and

wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor.

4. The semiconductor device according to claim 1 , further comprising a fifth transistor,

wherein a gate of the second transistor is electrically connected to one of a source and a drain of the fifth transistor, and

wherein a gate of the fourth transistor is electrically connected to the other of the source and the drain of the fifth transistor.

5. The semiconductor device according to claim 1 , further comprising a fifth transistor and a sixth transistor,

wherein a gate of the second transistor is electrically connected to one of a source and a drain of the fifth transistor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,

wherein the other of the source and the drain of the sixth transistor is electrically connected to a gate of the fourth transistor, and

wherein a gate of the fifth transistor is electrically connected to a gate of the sixth transistor.

Assignments (1)

Priority Claims (1)

Continuity (4)

References Cited (307)