3D semiconductor device and structure with metal layers
A semiconductor device, the device comprising: a first substrate; a first metal layer disposed over said substrate; a second metal layer disposed over said first metal layer; a first level comprising a plurality of transistors, said first level disposed over said second metal layer, wherein said plurality of transistors comprise single crystal silicon; a third metal layer disposed over said first level; a fourth metal layer disposed over said third metal layer, wherein said fourth metal layer is aligned to said first metal layer with a less than 200 nm alignment error; and a via disposed through said first level, wherein said via has a diameter of less than 450 nm, wherein said fourth metal layer provides a global power distribution, and wherein said via is directly connected to at least one of said plurality of transistors.
1. A semiconductor device, the device comprising:
a first substrate;
a first metal layer disposed over said substrate;
a second metal layer disposed over said first metal layer;
a first level comprising a plurality of transistors, said first level disposed over said second metal layer,
wherein said plurality of transistors comprise single crystal silicon;
a third metal layer disposed over said first level;
a fourth metal layer disposed over said third metal layer,
wherein said fourth metal layer is aligned to said first metal layer with a less than 200 nm alignment error; and
a via disposed through said first level,
wherein said via has a diameter of less than 450 nm,
wherein said fourth metal layer provides a global power distribution, and
wherein said via is directly connected to at least one of said plurality of transistors.
2. The device according to claim 1 ,
wherein said via comprises tungsten.
3. The device according to claim 1 ,
wherein said substrate comprises single crystal silicon.
4. The device according to claim 1 , further comprising:
connection pads disposed over portions of said fourth metal layer,
wherein said connection pads are capable to provide connections to external devices.
5. The device according to claim 1 ,
wherein a typical thickness of said first level is less than two microns.
6. The device according to claim 1 ,
wherein at least one of said plurality of transistors comprises a gate-all-around transistor structure.
7. The device according to claim 1 , further comprising:
a plurality of power decoupling capacitors.
8. A semiconductor device, the device comprising:
a substrate;
a first metal layer disposed over said first substrate;
a second metal layer disposed over said first metal layer;
a first level comprising a plurality of transistors, said first level disposed over said second metal layer,
wherein said plurality of transistors comprise single crystal silicon;
a third metal layer disposed over said first level;
a fourth metal layer disposed over said third metal layer,
wherein said fourth metal layer is aligned to said first metal layer with a less than 200 nm alignment error; and
a via disposed through said first level,
wherein at least a portion of said third metal layer and a portion of said fourth metal layer are part of heat removal paths, and
wherein said heat removal paths are designed to remove heat from said plurality of transistors to an external surface of said device.
9. The device according to claim 8 ,
wherein said via has a diameter of less than 450 nm.
10. The device according to claim 8 ,
wherein a typical thickness of said first level is less than two microns.
11. The device according to claim 8 ,
wherein said substrate comprises single crystal silicon.
12. The device according to claim 8 , further comprising:
a global power distribution network; and
a local power distribution network,
wherein said global power distribution network comprises said fourth metal layer,
wherein said local power distribution network comprises said third metal layer, and
wherein a typical thickness of said fourth metal layer is at least 50% greater than a typical thickness of said third metal.
13. The device according to claim 8 ,
wherein at least one of said plurality of transistors comprises a four-sided-gate transistor structure.
14. The device according to claim 8 , further comprising:
a plurality of power decoupling capacitors.
15. A semiconductor device, the device comprising:
a substrate;
a first metal layer disposed over said substrate;
a second metal layer disposed over said first metal layer;
a first level comprising a plurality of transistors, said first level disposed over said second metal layer,
wherein said plurality of transistors comprise single crystal silicon;
a third metal layer disposed over said first level;
a fourth metal layer disposed over said third metal layer,
wherein said fourth metal layer is aligned to said first metal layer with a less than 200 nm alignment error;
a global power distribution network; and
a local power distribution network,
wherein said global power distribution network comprises said fourth metal layer,
wherein said local power distribution network comprises said third metal layer, and
wherein a typical thickness of said fourth metal layer is at least 50% greater than a typical thickness of said third metal.
16. The device according to claim 15 ,
wherein said substrate comprises single crystal silicon.
17. The device according to claim 15 ,
wherein a typical thickness of said first level is less than two microns.
18. The device according to claim 15 ,
wherein at least one of said plurality of transistors comprises a gate-all-around transistor structure.
19. The device according to claim 15 , further comprising:
connection pads disposed above a portion of said fourth metal layer,
wherein said connection pads are capable to provide connection to external devices.
20. The device according to claim 15 , further comprising:
a plurality of power decoupling capacitors.