Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device
A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.
1 . A method of forming a semiconductor device, the method comprising:
providing a first planarized surface comprising a conductive material and a pore-filled dielectric;
recessing the conductive material with respect to the first planarized surface;
subsequent to recessing the conductive material, depositing an interlayer dielectric;
polishing the interlayer dielectric to form a second planarized surface comprising the pore-filled dielectric and the interlayer dielectric; and
removing pore-filling material from the pore-filled dielectric.
2 . The method of claim 1 , further comprising:
prior to depositing the interlayer dielectric, forming a conformal cap layer on the pore-filled dielectric and the conductive material.
3 . The method of claim 2 , wherein the conformal cap layer has a thickness of approximately 20 nm.
4 . The method of claim 2 , wherein the conformal cap layer has a thickness of approximately 5 nm.
5 . The method of claim 2 , wherein the conformal cap layer comprises silicon carbide.
6 . The method of claim 2 , wherein the conformal cap layer comprises silicon nitride.
7 . The method of claim 2 , wherein the conformal cap layer comprises silicon carbonitride.
8 . The method of claim 2 , wherein the polishing further comprises polishing the conformal cap layer to form the second planarized surface.
9 . The method of claim 1 , wherein providing the first planarized surface comprises: depositing the conductive material in a recessed portion of the pore-filled dielectric.
10 . The method of claim 1 , wherein removing the pore-filling material from the pore-filled dielectric comprises a thermal treatment.
11 . The method of claim 1 , wherein removing the pore-filling material from the pore-filled dielectric comprises an ultraviolet, UV, treatment.
12 . The method of claim 1 , wherein the polishing comprises chemical-mechanical polishing, CMP.
13 . The method of claim 8 , wherein the polishing comprises chemical-mechanical polishing, CMP.
14 . The method of claim 1 , wherein recessing the conductive material comprises etching.
15 . The method of claim 1 , further comprising: forming a fully-aligned via in a region where the conductive material is recessed.
16 . The method of claim 2 , wherein the second planarized surface further comprises a portion of the conformal cap layer.
17 . The method of claim 1 , wherein the pore-filling material comprises a thermoplastic material.
18 . The method of claim 1 , wherein the pore-filled dielectric comprises at least one of: methyl silsesquioxane, hydrogen silsesquioxane, benzocyclobutene, silica, and an aromatic thermoset polymer.
19 . The method of claim 1 , wherein the pore-filled dielectric has a thickness of 60 nm to 200 nm.
20 . The method of claim 1 , wherein the pore-filled dielectric has a porosity of approximately 0.1 vol. % to approximately 50 vol. %.