Apparatuses and methods for configurable ECC modes
Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.
1 . An apparatus comprising:
a first data column plane comprising a first bit line;
a second data column plane comprising a second bit line;
an extra column plane comprising a third bit line;
a column decoder configured to, as part of an access operation, activate the first bit line, and activate at least one of the second bit line or the third bit line; and
an error correction code (ECC) circuit configured to, as part of the access operation:
access data bits along the first bit line,
in a first mode, access additional data bits along the second bit line and parity bits along the third bit line, and
in a second mode, access the parity bits along the activated one of the second or third bit line.
2 . The apparatus of claim 1 , wherein, as part of a second access operation:
the column decoder is configured to activate a fourth bit line of the second data column plane and activate one of a fifth bit line of the first data column plane or a sixth bit line of the extra column plane; and
the ECC circuit is configured to access second data bits along the fourth bit line and parity bits along the activated one of the fifth or sixth bit line.
3 . The apparatus of claim 2 , wherein the column decoder is configured to activate the first bit line during the access operation based on a column select bit of a first column address having a first value specifying that the data bits are stored at the first data column plane and to activate the fourth bit line during the second access operation based on the column select bit of a second column address having a second value specifying that the second data bits are stored at the first data column plane.
4 . The apparatus of claim 1 , wherein the column decoder is configured to selectively activate the one of the second bit line or the third bit line bit lines based on a received column address.
5 . The apparatus of claim 1 , wherein the first data column plane has a same number of memory cells as the extra column plane.
6 . The apparatus of claim 1 , further comprising an input/output circuit configured to receive the data bits from the ECC circuit if the access operation is a read operation and configured to provide the data bits to the ECC circuit if the access operation is a write operation.
7 . The apparatus of claim 1 , wherein the ECC circuit is configured to locate and correct errors in the data bits based on the parity bits when the access operation is a read operation.
8 . The apparatus of claim 1 , wherein responsive to a column address received as part of the access operation, the column decoder is configured to provide a column select signal with a first value to the first data column plane, and to provide one of a second column select signal with a second value to the second data column plane or a third column select signal with the first value to the extra column plane.
9 . The apparatus of claim 8 , wherein the apparatus is a memory device operating in an x4 mode.
10 . An apparatus comprising:
a memory bank comprising:
a first plurality of column planes;
a second plurality of column planes; and
an extra column plane; and
a column decoder configured to select the first or the second plurality of column planes based on a column address received as part of an access operation, wherein as part of the access operation data bits are accessed in the selected one of the first or the second plurality of column planes, and based on the column address, parity bits are accessed in one of the extra column plane or the non-selected one of the first or the second plurality of column planes, wherein in a first mode, additional data bits are accessed in the other one of the first or the second plurality of column planes and the parity bits are accessed in the extra column plane, and wherein in a second mode, the parity bits are accessed in the second plurality of column planes or the extra column plane.
11 . The apparatus of claim 10 , further comprising an error correction code (ECC) circuit configured to locate and correct errors in the data bits based on the parity bits.
12 . The apparatus of claim 10 , wherein the ECC circuit is configured to perform single error correction, double error detection (SECDED) based on the parity bits and the data bits in the second mode.
13 . The apparatus of claim 12 , wherein the column decoder is configured to decode the column address to determine whether the parity bits are stored at the extra column plane or the non-selected one of the first or the second plurality of column planes.
14 . The apparatus of claim 10 , wherein the column decoder is configured to select the one of the first plurality of column planes or the second plurality of column planes based on a column plane select bit of the column address.
15 . A method comprising:
receiving a column address as part of an access operation;
accessing data bits from columns in a first portion of a plurality of data column planes as part of the access operation based on the column address; and
based on the column address, accessing parity bits from one of a column in a column plane not in the first portion of the plurality of data column planes or in a column of an extra column plane as part of the access operation,
wherein in a first mode, accessing additional data bits from the one of the column in the column plane in the first portion of the plurality of data column planes and the parity data bits in the column of the extra column plane, and
wherein in a second mode, accessing the parity data bits from the one of the volume in the column plane not in the first portion of the plurality of data column planes or in the column of the extra column plane.
16 . The method of claim 15 , further comprising correcting an error in the data bits based on the parity bits with an error correction code (ECC) circuit.
17 . The method of claim 15 , further comprising performing single error correction, double error detection (SECDED) with an error correction code (ECC) circuit using the parity bits in the second mode.
18 . The method of claim 15 , further comprising accessing the parity bits from the column in the column plane not in the first portion of the plurality of data column planes in response to the column address having a first value.
19 . The method of claim 18 , further comprising accessing the parity bits from the column in the extra column plane in response to the column address having a second value.
20 . The method of claim 19 , further comprising:
receiving a second column address as part of a second access operation;
accessing second data bits from a second portion of the plurality of data column planes non-overlapping with the first portion of the plurality of data column planes as part of the second access operation based on the second column address; and
based on the second column address, accessing parity bits from one of a column in the first portion of the plurality of data column planes or in a column of the extra column plane as part of the access operation.