Apparatus for non-volatile random access memory stacks
A memory structure is provided, including a NAND block comprising a plurality of oxide layers, the plurality of layers forming a staircase structure at a first edge of the NAND block, a plurality of vias disposed on the staircase structure of NAND block, two or more of plurality of vias terminating along a same plane, a plurality of first bonding interconnects disposed on the plurality of vias, a plurality of bitlines extending across the NAND block, and a plurality of second bonding interconnects disposed along the bitlines. The memory structure may be stacked on another of the memory structure to form a stacked memory device.
1. A memory structure, comprising:
a memory array comprising a plurality of vertical channels extending in a vertical direction through a stack comprising a plurality of wordline layers alternating with a plurality of insulating layers, wherein the vertical channels are electrically connected to a plurality of bitlines extending over the memory array in a horizontal direction; and
a plurality of first bonding interconnect structures electrically connected to the wordline layers and a plurality of second bonding interconnect structures electrically connected to the bitlines, wherein the first and second bonding interconnect structures are disposed at substantially the same vertical level over the bitlines to direct bond to an integrated circuit (IC) structure above the memory array without using an adhesive material.
2. The memory structure of claim 1 , wherein one or both of the first and second bonding interconnect structures are embedded in a dielectric material to form a bonding surface configured for hybrid direct bonding with the IC structure.
3. The memory structure of claim 1 , wherein the memory array comprises a NAND flash memory array.
4. The memory structure of claim 1 , wherein the stack forms a staircase structure with successive wordline layers having end portions that successively decrease in lateral lengths.
5. The memory structure of claim 4 , wherein the wordline layers are electrically connected to the first bonding structures by wordline vias extending in the vertical direction at the end portions.
6. The memory structure of claim 5 , wherein the first bonding interconnect structures are physically formed on or over the wordline vias.
7. The memory structure of claim 5 , further comprising edge wordline vias that are disposed laterally outside of the staircase structure, and wherein the first bonding interconnect structures are physically formed on or over the edge wordline vias.
8. The memory structure of claim 5 , further comprising bitline vias connected contacted to the bitlines and extending vertically downward across the stack.
9. The memory structure of claim 1 , wherein the IC structure comprises logic circuitry bonded to the memory array through the first and second bonding interconnect structures.
10. The memory structure of claim 9 , wherein the stack further comprises select gate layers electrically connected and controlled by the logic circuitry.
11. The memory structure of claim 1 , wherein a silicon substrate has been removed from the memory structure such that the memory array is not disposed over the silicon substrate.
12. A memory device, comprising:
a memory array comprising a plurality of vertical channels extending in a vertical direction through a stack comprising a plurality of wordline layers alternating with a plurality of insulating layers, wherein the vertical channels are electrically connected to a plurality of bitlines extending over the memory array in a horizontal direction;
a plurality of first bonding interconnect structures electrically connected to the wordline layers and disposed at a vertical level over the bitlines; and
a further integrated circuit (IC) structure stacked on and direct bonded to the memory array through the first bonding interconnect structures without using an adhesive material.
13. The memory device of claim 12 , further comprising a plurality of second bonding interconnect structures electrically connected to the bitlines, wherein the first and second bonding interconnect structures substantially coterminate at the vertical level over the bitlines.
14. The memory device of claim 12 , wherein the further IC structure comprises logic circuitry configured to control the memory array.
15. The memory device of claim 14 , wherein the stack further comprises select gate layers electrically connected to the logic circuitry.
16. The memory device of claim 12 , wherein the further IC structure is a second memory array.
17. The memory device of claim 16 , wherein the second memory array comprises a second plurality of vertical channels extending in the vertical direction through a second stack comprising a plurality of second wordline layers alternating with a second plurality of insulating layers, wherein the second vertical channels are electrically connected to a second plurality of bitlines extending over the second memory array in the horizontal direction.
18. The memory device of claim 12 , wherein the stack forms a staircase structure with successive wordline layers having end portions that successively decrease in lateral lengths.
19. The memory device of claim 18 , wherein the wordline layers are electrically connected to the first bonding interconnect structures by wordline vias extending in the vertical direction at the end portions.
20. The memory device of claim 19 , wherein the first bonding interconnect structures are physically formed on or over the wordline vias.
21. The memory device of claim 18 , wherein the memory array further comprises edge wordline vias that are physically disposed laterally outside of the staircase structure, and wherein the first bonding interconnect structures are physically formed on or over the edge wordline vias.