Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
Mitigating surface damage of probe pads in preparation for direct bonding of a substrate is provided. Methods and layer structures prepare a semiconductor substrate for direct bonding processes by restoring a flat direct-bonding surface after disruption of probe pad surfaces during test probing. An example method fills a sequence of metals and oxides over the disrupted probe pad surfaces and builds out a dielectric surface and interconnects for hybrid bonding. The interconnects may be connected to the probe pads, and/or to other electrical contacts of the substrate. A layer structure is described for increasing the yield and reliability of the resulting direct bonding process. Another example process builds the probe pads on a next-to-last metallization layer and then applies a direct bonding dielectric layer and damascene process without increasing the count of mask layers. Another example process and related layer structure recesses the probe pads to a lower metallization layer and allows recess cavities over the probe pads.
1. A structure for direct bonding, including a buried probe pad in a substrate for microelectronics, the structure comprising:
the probe pad formed in a probe pad metal layer of the substrate, the probe pad having an upper surface sized for test contact;
an insulating material formed over the upper surface of the probe pad metal layer;
a plurality of operational interconnects at least partially embedded in the insulating material;
wherein the insulating material and the operational interconnects are part of a bonding surface prepared for direct hybrid bonding; and
wherein the operational interconnects are electrically and physically connected to the probe pad metal layer through the insulating material without physically and electrically connecting through the upper surface of the probe pad.
2. The structure of claim 1 , wherein the probe pad comprises at least one mark from probing the probe pad.
3. The structure of claim 2 , wherein the at least one mark comprises at least one protrusion.
4. The structure of claim 2 , further comprising a copper interconnect through the insulating material.
5. The structure of claim 2 , wherein the probe pad metal layer comprises aluminum and the operational interconnects comprise copper.
6. The structure of claim 2 , wherein the probe pad metal layer is a second-to-last metallization layer of the substrate.
7. The structure of claim 2 , wherein the probe pad metal layer is a third-to-last metallization layer of the substrate.
8. The structure of claim 2 , wherein the operational interconnects include a first operational interconnect on a first lateral side of the probe pad and a second operational interconnect on a second lateral side of the probe pad opposite the first lateral side.
9. The structure of claim 2 , further comprising
a second insulating material on an opposite side of the substrate from the insulating material;
through-silicon vias (TSVs) in the substrate; and
second interconnects through the second insulating material such that the second insulating material comprises a second direct hybrid bonding surface.
10. A bonded structure, including a buried probe pad in a first substrate for microelectronics, the structure comprising:
the first substrate including the probe pad formed in a probe pad metal layer, the probe pad having an upper surface sized for test contact;
a first insulating structure entirely covering the upper surface of the probe pad;
a first operational interconnect for direct bonding, the first operational interconnect electrically connected through the first insulating structure to a first feature in the probe pad metal layer; and
a second substrate including a second insulating structure and a second operational interconnect in the second insulating structure, wherein the second insulating structure is directly bonded to the first insulating structure of the first substrate, and the first operational interconnect is directly bonded to the second operational interconnect, such that an interface between the first and second substrates is a direct hybrid bonding interface.
11. The bonded structure of claim 10 , wherein the probe pad comprises at least one mark from probing the probe pad.
12. The bonded structure of claim 11 , wherein the at least one mark comprises at least one protrusion.
13. The bonded structure of claim 11 , wherein the first feature in the probe pad metal layer is positioned on a first lateral side of the probe pad, further comprising a third operational interconnect connected to a second feature in the probe pad metal layer through the first insulating structure, the second feature positioned on a second lateral side of the probe pad opposite the first lateral side, and the third operational interconnect being directly bonded to a fourth operational interconnect of the second substrate.
14. The bonded structure of claim 11 , wherein the probe pad metal layer comprises aluminum.
15. The bonded structure of claim 14 , wherein the first operational interconnect comprises copper and a barrier layer.
16. The bonded structure of claim 15 , wherein the barrier layer comprises tantalum.
17. The bonded structure of claim 11 , wherein the probe pad metal layer is a second-to-last metallization layer of the first substrate.
18. The bonded structure of claim 11 , wherein the probe pad metal layer is a third-to-last metallization layer of the first substrate and at least a portion of the first operational interconnect is formed in a second-to-last metallization layer and a last metallization layer of the first substrate.
19. A semiconductor device for a direct hybrid bonding process, comprising:
a probe pad in a metal layer of a semiconductor substrate, a contact surface of the probe pad comprising a mark characteristic of contact with a test probe, the contact surface being entirely covered by an insulating material;
an insulating layer of the insulating material over the contact surface of the probe pad, the insulating layer including openings over electrical contacts in the metal layer adjacent to the probe pad; and
a metal in the openings;
wherein top surfaces of the metal and the insulating layer provide a direct hybrid bonding surface with metal and nonmetal regions for the direct hybrid bonding process.
20. The semiconductor device of claim 19 , wherein the electrical contacts comprise a first electrical contact and a second electrical contact on opposite lateral sides of the probe pad.
21. The semiconductor device of claim 19 , further comprising a second metal layer on the probe pad below the insulating layer.
22. The semiconductor device of claim 19 , wherein the metal layer of the probe pad is a second-to-last metallization layer of the substrate, and the metal in the openings is a last metallization layer of the substrate.
23. The semiconductor device of claim 19 , wherein the probe pad comprises a second metal composition different from a first metal composition in the openings.
24. The semiconductor device of claim 23 , wherein the second metal composition comprises aluminum and the first metal composition in the openings comprises copper.
25. A method of preparing a semiconductor substrate for direct hybrid bonding, comprising:
providing the semiconductor substrate, including a metal layer comprising a plurality of conductive features;
testing circuitry of the semiconductor substrate including contacting a probe pad of the conductive features with a test probe;
after testing, depositing at least one insulating layer above the conductive features;
patterning the at least one insulating layer to form openings;
providing metal in the openings to form operational bonding pads electrically connected to at least some of the conductive features without electrically connecting to the probe pad through an upper contact surface of the probe pad; and
planarizing the metal and the at least one insulating layer to provide a surface having metal and nonmetal regions for direct hybrid bonding, the metal regions including the operational bonding pads.
26. The method of claim 25 , further comprising depositing a metal material on the probe pad after testing and before depositing the at least one insulating layer.
27. The method of claim 25 , wherein depositing the at least one insulating layer comprises depositing on a surface of the probe pad contacted by the test probe.
28. The method of claim 25 , further comprising providing electrical connection through multiple insulating layers of the at least one insulating layer between the metal in the openings and the at least some of the conductive features.