Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer
An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.
1 . A layered semiconductor construct comprising, in sequence: a semiconductor substrate, a buried stressor layer comprising polycrystalline silicon under compressive stress disposed on the semiconductor substrate, an insulating layer disposed on the buried stressor layer, and a surface semiconductor layer disposed on the insulating layer, wherein the surface semiconductor layer includes an active region that is disposed between a pair of trenches, the trenches extending through the surface semiconductor layer, the insulating layer, and the buried stressor layer and being displaced laterally from one another by a distance sufficiently small that relaxation of the buried stressor layer occurs across an entire lateral extent of a portion of the insulating layer between the trenches.
2 . The layered semiconductor construct of claim 1 , wherein the surface semiconductor layer comprises Si.
3 . The layered semiconductor construct of claim 1 , wherein the surface semiconductor layer comprises Ge.
4 . The layered semiconductor construct of claim 1 , wherein the surface semiconductor layer comprises a compound semiconductor.
5 . The layered semiconductor construct of claim 1 , wherein the insulating layer is a layer of a silicon oxide.
6 . The layered semiconductor construct of claim 1 , wherein the semiconductor substrate and the surface semiconductor layer each comprise the same semiconductor.
7 . The layered semiconductor construct of claim 1 , wherein the surface semiconductor layer has a thickness of up to 50 nanometers.
8 . The layered semiconductor construct of claim 2 , wherein the semiconductor substrate and the surface semiconductor layer each comprise the same semiconductor.
9 . The layered semiconductor construct of claim 3 , wherein the semiconductor substrate and the surface semiconductor layer each comprise the same semiconductor.
10 . The layered semiconductor construct of claim 4 , wherein the semiconductor substrate and the surface semiconductor layer each comprise the same semiconductor.
11 . The layered semiconductor construct of claim 5 , wherein the semiconductor substrate and the surface semiconductor layer each comprise the same semiconductor.
12 . The layered semiconductor construct of claim 2 , wherein the surface semiconductor layer has a thickness of up to 50 nanometers.
13 . The layered semiconductor construct of claim 3 , wherein the surface semiconductor layer has a thickness of up to 50 nanometers.
14 . The layered semiconductor construct of claim 4 , wherein the surface semiconductor layer has a thickness of up to 50 nanometers.
15 . The layered semiconductor construct of claim 5 , wherein the surface semiconductor layer has a thickness of up to 50 nanometers.
16 . The layered semiconductor construct of claim 6 , wherein the surface semiconductor layer has a thickness of up to 50 nanometers.
17 . The layered semiconductor construct of claim 1 , wherein the surface semiconductor layer is tensile strained across an entire lateral extent of a portion of the surface semiconductor layer between the trenches.
18 . The layered semiconductor construct of claim 1 , wherein the active region of the surface semiconductor layer is tensile strained across a partial lateral extent of a portion of the active region between the trenches.
19 . The layered semiconductor construct of claim 1 , wherein the active region of the surface semiconductor layer includes a channel region of a field effect transistor.
20 . The layered semiconductor construct of claim 17 , wherein the tensile strained portion of the surface semiconductor layer includes a channel region of a field effect transistor.
21 . The layered semiconductor construct of claim 1 , wherein the insulating layer has a thickness of up to 50 nanometers.
22 . The layered semiconductor construct of claim 1 , wherein tensile strain in the surface semiconductor layer between the trenches is non-uniform across its extent between the trenches.
23 . The layered semiconductor construct of claim 1 , wherein the buried stressor layer comprises a back gate of a transistor device formed at least partially in the active region of the surface semiconductor layer.
24 . The layered semiconductor construct of claim 1 , wherein the buried stressor layer has an in-plane stress of magnitude greater than 200 megaPascal.
25 . The layered semiconductor construct of claim 1 , wherein the buried stressor layer has an in-plane stress of magnitude greater than greater than 1 gigaPascal.
26 . The layered semiconductor construct of claim 1 , wherein the buried stressor layer comprising polycrystalline silicon is formed by annealing a layer of doped amorphous silicon.
27 . The layered semiconductor construct of claim 26 , wherein the amorphous silicon is doped by ion implantation of arsenic atoms.