Granted Patent B2

US 12,242,122 · App. 18/632,658 · Granted Mar 4, 2025

Inventors: Philip Winterbottom (San Jose, CA); David Lazovsky (Los Gatos, CA); Ankur Aggarwal (Pleasanton, CA); Martinus Bos (San Jose, CA); Subal Sahni (La Jolla, CA)

Assignee: Celestial AI Inc.

G02B6/4295G02B6/4246G02B6/428G02B6/43G02F1/0157G02B6/4245

Abstract

Claims (26)

1. A package comprising:

a first die comprising a first compute element and/or a first memory element, and a first region;

a second die comprising a second compute element and/or a second memory element, and a second region; and

a first bridging element bridging the first die and the second die;

wherein the first bridging element comprises:

a first interconnect region and a second interconnect region for electrical coupling to the first die and to the second die;

a first photonic path from the first interconnect region to the second interconnect region; and

a second photonic path from the second interconnect region to the first interconnect region;

and wherein:

a first portion (MOD 1 , PD 1 ) of a photonic transceiver resides in a photonic integrated circuit (PIC) and is coupled between the first interconnect region on one side and the first photonic path and the second photonic path on another side, and wherein a second portion of the photonic transceiver resides in an electric integrated circuit (EIC), the first and the second portions being coupled via an electrical interconnect less than two millimeters (2 mm) in length.

2. The package of claim 1 , wherein a second portion (DRV1, TIA1) of the photonic transceiver resides in an AMS block proximate to a memory element or a compute element in a first region in the first die or in a second region in the second die, and wherein the second portion includes a driver (DRV1) and a transimpedance amplifier (TIA1).

3. The package of claim 2 , wherein the AMS block is adjacent to an edge of the first region or to an edge of the second region.

4. The package of claim 2 , wherein the first portion and the second portion of the photonic transceiver are coupled via an electrical interconnect less than about two millimeters (2 mm) in length.

5. The package of claim 2 , wherein the first region includes at least one of a memory, a cache memory, other shared memory, a network on-chip crossbar, a switch, a routing mechanism, or a memory controller.

6. The package of claim 2 , wherein the second region includes at least one of a memory, a cache memory, other shared memory, a network on-chip crossbar, a switch, a routing mechanism, or a memory controller.

7. The package of claim 2 , wherein:

the first region is located centrally in the first die to even out latencies between the first compute element and the first region.

8. The package of claim 2 , wherein:

the second region is located centrally in the second die to even out latencies between the second compute element and the second region.

9. The package of claim 2 , wherein the first region intersects a center of the first die.

10. The package of claim 2 , wherein the second region intersects a center of the second die.

11. The package of claim 1 , wherein the first die and/or the second die includes multiple compute elements and/or multiple memory elements.

12. The package of claim 2 , wherein the compute element on the first die is adjacent to an AMS block in or near the first region and the memory element on the second die is adjacent to an AMS block in or near the second region and signals between the compute element and the memory element travel substantially via one or more photonic paths in the first bridging element.

13. The package of claim 2 , wherein multiple AMS blocks are arranged along an outer edge of the first region, and at least one of the multiple AMS blocks is located proximate to a compute element.

14. The package of claim 1 , wherein a memory element is one of a static random-access memory (RAM) (an SRAM), a dynamic RAM (DRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and a conductive bridging RAM (CBRAM).

15. The package of claim 1 , wherein a compute element is one of a central processing unit (CPU), a graphic processing unit (GPU), and a tensor processing unit (TPU).

Assignments (2)

Continuity (6)

References Cited (295)

Cited By (11)

US 12,399,333 US 12,436,346 US 12,442,997 US 12,442,998 US 12,442,999 US 12,443,000 US 12,468,103 US 12,571,969 US 12,674,948 US 12,674,949 US 12,699,240