Display device
A display device with a narrower frame can be provided. In the display device, a first layer, a second layer, and a third layer are provided to be stacked. The first layer includes a gate driver circuit and a data driver circuit, the second layer includes a demultiplexer circuit, and the third layer includes a display portion. In the display portion, pixels are arranged in a matrix, an input terminal of the demultiplexer circuit is electrically connected to the data driver circuit, and an output terminal of the demultiplexer circuit is electrically connected to some of the pixels. The gate driver circuit and the data driver circuit are provided to include a region overlapping some of the pixels. The gate driver circuit and the data driver circuit have a region where they are not strictly separated from each other and overlap each other. Five or more gate driver circuits and five or more data driver circuits can be provided.
1 . A display device comprising:
a first layer comprising a gate driver circuit and a data driver circuit;
a second layer stacked on the first layer, the second layer comprising at least first and second demultiplexer circuits; and
a third layer stacked on the second layer, the third layer comprising a display portion having a plurality of pixels arranged in a matrix,
wherein the first and second demultiplexer circuits are electrically connected to the data driver circuit and the display portion,
wherein at least one of the gate driver circuit and the data driver circuit includes a first transistor having a channel formation region comprising silicon, and
wherein each of the plurality of pixels includes a second transistor having a channel formation region comprising a metal oxide.
2 . The display device according to claim 1 , wherein the display portion overlaps with the first and second demultiplexer circuits, the gate driver circuit, and the data driver circuit.
3 . The display device according to claim 1 , wherein the gate driver circuit comprises a region overlapping the data driver circuit.
4 . The display device according to claim 1 ,
wherein the metal oxide comprises indium.
5 . The display device according to claim 1 , further comprising a first circuit,
wherein the first circuit is electrically connected to a plurality of second circuits included in the data driver circuit, and
wherein the first circuit is not overlapped with the display portion.
6 . The display device according to claim 5 ,
wherein the first circuit is configured to generate a plurality of potentials with different levels from each other, and
wherein the plurality of second circuits are configured to receive image data and output any of the plurality of potentials generated by the first circuit based on digital value of the image data.
7 . The display device according to claim 5 , wherein the number of the plurality of second circuits is smaller than the number of columns of the plurality of pixels arranged in the matrix.
8 . A display device comprising:
a first layer comprising a gate driver circuit and at least first and second data driver circuits;
a second layer stacked on the first layer, the second layer comprising at least first and second demultiplexer circuits; and
a third layer stacked on the second layer, the third layer comprising at least first and second display portions,
wherein each of the first and second display portions comprises a plurality of pixels arranged in a matrix,
wherein the first demultiplexer circuit is electrically connected to the first data driver circuit and the first display portion,
wherein the second demultiplexer circuit is electrically connected to the second data driver circuit and the second display portion,
wherein at least one of the gate driver circuit and the first and second data driver circuits includes a first transistor having a channel formation region comprising silicon, and
wherein each of the plurality of pixels includes a second transistor having a channel formation region comprising a metal oxide.
9 . The display device according to claim 8 ,
wherein the first display portion overlaps with the first demultiplexer circuit, the gate driver circuit, and the first data driver circuit, and
wherein the second display portion overlaps with the second demultiplexer circuit, and the second data driver circuit.
10 . The display device according to claim 8 , wherein the gate driver circuit comprises a region overlapping the first data driver circuit.
11 . The display device according to claim 8 ,
wherein the metal oxide comprises indium.
12 . The display device according to claim 8 , further comprising a first circuit electrically connected to the first and second data driver circuits,
wherein each of the first and second data driver circuits includes a plurality of second circuits electrically connected to the first circuit, and
wherein the first circuit is not overlapped with the first and second display portions.
13 . The display device according to claim 12 ,
wherein the first circuit is configured to generate a plurality of potentials with different levels from each other, and
wherein the plurality of second circuits are configured to receive image data and output any of the plurality of potentials generated by the first circuit based on digital value of the image data.
14 . The display device according to claim 12 , wherein the number of the plurality of second circuits is smaller than the number of columns of the plurality of pixels arranged in the matrix.
15 . A display device comprising:
a first layer comprising at least first and second gate driver circuits and at least first and second data driver circuits;
a second layer stacked on the first layer, the second layer comprising at least first and second demultiplexer circuits; and
a third layer stacked on the second layer, the third layer comprising at least first and second display portions,
wherein each of the first and second display portions comprises a plurality of pixels arranged in a matrix,
wherein the first demultiplexer circuit is electrically connected to the first data driver circuit and the first display portion,
wherein the second demultiplexer circuit is electrically connected to the second data driver circuit and the second display portion,
wherein at least one of the first and second gate driver circuits and the first and second data driver circuits includes a first transistor having a channel formation region comprising silicon, and
wherein each of the plurality of pixels includes a second transistor having a channel formation region comprising a metal oxide.
16 . The display device according to claim 15 ,
wherein the first display portion overlaps with the first demultiplexer circuit, the first gate driver circuit, and the first data driver circuit, and
wherein the second display portion overlaps with the second demultiplexer circuit, the second gate driver circuit, and the second data driver circuit.
17 . The display device according to claim 15 ,
wherein the first gate driver circuit comprises a region overlapping the first data driver circuit, and
wherein the second gate driver circuit comprises a region overlapping the second data driver circuit.
18 . The display device according to claim 15 ,
wherein the metal oxide comprises indium.
19 . The display device according to claim 15 , further comprising a first circuit electrically connected to the first and second data driver circuits,
wherein each of the first and second data driver circuits includes a plurality of second circuits electrically connected to the first circuit, and
wherein the first circuit is not overlapped with the first and second display portions.
20 . The display device according to claim 19 ,
wherein the first circuit is configured to generate a plurality of potentials with different levels from each other, and
wherein the plurality of second circuits are configured to receive image data and output any of the plurality of potentials generated by the first circuit based on digital value of the image data.
21 . The display device according to claim 19 ,
wherein the number of the plurality of second circuits is smaller than the number of columns of the plurality of pixels arranged in the matrix.