3D semiconductor devices and structures with metal layers
A semiconductor device including: a first level including a first single crystal silicon layer, a plurality of first transistors, and input/output circuits; a first metal layer; a second metal layer which includes a power delivery network; where interconnection of the plurality of first transistors includes the first and second metal layers; a second level including a plurality of metal gate second transistors and first array of memory cells, disposed over the first level; a third level including a plurality of metal gate third transistors and a second array of memory cells, disposed over the second level; a via disposed through the second and third levels; a third metal layer disposed over the third level; a fourth metal layer disposed over the third metal layer; and a fourth level disposed over the fourth metal layer and including a second single crystal silicon layer.
1. A semiconductor device, the semiconductor device comprising:
a first level comprising a first single crystal silicon layer and a plurality of first transistors;
a first metal layer;
a second metal layer,
wherein interconnection of said plurality of first transistors comprises said first metal layer and said second metal layer;
a second level comprising a plurality of second transistors, said second level disposed over said first level;
a third level comprising a plurality of third transistors, said third level disposed over said second level;
a third metal layer disposed over said third level;
a fourth metal layer disposed over said third metal layer;
a fourth level comprising a second single crystal silicon layer,
wherein said fourth level is disposed over said fourth metal layer,
wherein each of said plurality of second transistors comprises a metal gate,
wherein said second metal layer comprises a power delivery network; and
a via disposed through said second level and through said third level,
wherein each of said plurality of third transistors comprises a metal gate,
wherein said second level comprises a first array of memory cells,
wherein said third level comprises a second array of memory cells, and
wherein said first level comprises input and output (“IO”) circuits as part of connections of said device to external devices.
2. The semiconductor device according to claim 1 , further comprising:
a connection path from said third metal layer and said second metal layer,
wherein said connection path comprises said via.
3. The semiconductor device according to claim 1 , further comprising:
a power delivery path to at least one of said plurality of second transistors,
wherein said power delivery path comprises at least a part of said second metal layer.
4. The semiconductor device according to claim 1 ,
wherein at least one of said metal gates comprises tungsten.
5. The semiconductor device according to claim 1 , further comprising:
memory control circuits,
wherein said memory control circuits comprise a portion of said plurality of first transistors.
6. The semiconductor device according to claim 1 , further comprising:
power control circuits,
wherein said power control circuits comprise a portion of said plurality of first transistors.
7. The semiconductor device according to claim 1 , further comprising:
a power delivery path to at least one of said plurality of second transistors,
wherein said power delivery path comprises said via.
8. A semiconductor device, the semiconductor device comprising:
a first level comprising a first single crystal silicon layer and a plurality of first transistors;
a first metal layer;
a second metal layer,
wherein interconnection of said plurality of first transistors comprises said first metal layer and said second metal layer;
a second level comprising a plurality of second transistors, said second level disposed over said first level;
a third level comprising a plurality of third transistors, said third level disposed over said second level;
a third metal layer disposed over said third level;
a fourth metal layer disposed over said third metal layer; and
a via disposed through said second level and through said third level as part of a connection path between said third metal layer to said second metal layer,
wherein each of said plurality of second transistors comprises a metal gate,
wherein at least one of said metal gates comprises tungsten,
wherein said second level comprises a first array of memory cells,
wherein said third level comprises a second array of memory cells,
wherein formation of said plurality of second transistors comprises a first lithography step, and
wherein formation of said plurality of third transistors comprises a second lithography step.
9. The semiconductor device according to claim 8 ,
wherein said first level comprises input and output (“IO”) circuits as part of connections of said device to external devices.
10. The semiconductor device according to claim 8 , further comprising:
a power delivery path to at least one of said plurality of second transistors,
wherein said power delivery path comprises at least a part of said second metal layer.
11. The semiconductor device according to claim 8 ,
wherein at least one of said metal gates comprises tungsten.
12. The semiconductor device according to claim 8 , further comprising:
memory control circuits,
wherein said memory control circuits comprise a portion of said plurality of first transistors.
13. The semiconductor device according to claim 8 , further comprising:
power control circuits,
wherein said power control circuits comprise a portion of said plurality of first transistors.
14. The semiconductor device according to claim 8 , further comprising:
a power delivery path to at least one of said plurality of second transistors,
wherein said power delivery path comprises said via.
15. A semiconductor device, the semiconductor device comprising:
a first level comprising a first single crystal silicon layer and a plurality of first transistors;
a first metal layer;
a second metal layer,
wherein interconnection of said plurality of first transistors comprises said first metal layer and said second metal layer;
a second level comprising a plurality of second transistors, said second level disposed over said first level;
a third level comprising a plurality of third transistors, said third level disposed over said second level;
a third metal layer disposed over said third level;
a fourth metal layer disposed over said third metal layer;
a fourth level comprising a second single crystal silicon layer,
wherein said fourth level is disposed over said fourth metal layer,
wherein each of said plurality of second transistors comprises a metal gate,
wherein said second metal layer comprises a power delivery network; and
a via disposed through said second level and through said third level,
wherein each of said plurality of third transistors comprises a metal gate,
wherein said second level comprises a first array of memory cells,
wherein said third level comprises a second array of memory cells,
wherein said first level comprises power control circuits controlling power delivery to said second transistors, and
wherein said power control circuits comprise a portion of said plurality of said first transistors.
16. The semiconductor device according to claim 15 , further comprising:
a connection path from said third metal layer and said second metal layer,
wherein said connection path comprises said via.
17. The semiconductor device according to claim 15 ,
wherein said first level comprises input and output (“IO”) circuits as part of connections of said device to external devices.
18. The semiconductor device according to claim 15 ,
wherein at least one of said metal gates comprises tungsten.
19. The semiconductor device according to claim 15 , further comprising:
memory control circuits,
wherein said memory control circuits comprise a portion of said plurality of first transistors.
20. The semiconductor device according to claim 15 , further comprising:
a power delivery path to at least one of said plurality of second transistors,
wherein said power delivery path comprises said via.