Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation
View Patent ↗Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.
1. An apparatus comprising:
a phase interpolation control signal generator configured to generate a multi-bit control signal;
four weighted AND gates, each weighted AND gate configured to receive a respective pairwise combination of (i) a reference signal or its complement and (ii) a local oscillator signal or its complement, each weighted AND gate having a control input configured to receive a portion of the multi-bit control signal to control an amount of source current or sink current to an output node; and
a low pass filter connected to the output node configured to generate a local oscillator control signal by filtering the sourced and sunk currents on the output node.
2. The apparatus of claim 1 , wherein the four weighted AND gates comprise first and second PMOS-based AND gates configured to source current to the output node, the first and second PMOS-based AND gates configured to receive the pairwise combinations of (i) the reference signal and the local oscillator signal and (ii) the complement of the reference signal and the complement of the local oscillator signal, respectively.
3. The apparatus of claim 1 , wherein the four weighted AND gates comprise first and second NMOS-based AND gates configured to sink current from the output node, the first and second NMOS-based AND gates configured to receive the pairwise combinations of (i) the reference signal and the complement of the local oscillator signal and (ii) the complement of the reference signal and the local oscillator signal, respectively.
4. The apparatus of claim 1 , wherein the low pass filter comprises a capacitor configured to charge and discharge responsive to the sourced and sunk currents, respectively.
5. The apparatus of claim 1 , further comprising four additional weighted AND gates, each additional weighted AND gate configured to receive a respective pairwise combination of (i) the reference signal or its complement and (ii) a second local oscillator signal or its complement, each additional weighted AND gate having a control input configured to receive a portion of the multi-bit control signal to control an amount of source current or sink current to the output node.
6. The apparatus of claim 5 , wherein the local oscillator control signal corresponds to a summation of currents sourced to and sunk from the output node via the four weighted AND gates and the four additional weighted AND gates.
7. The apparatus of claim 1 , wherein the control input of each weighted AND gate comprises a resistor bank configured to receive the portion of the multi-bit control signal.
8. The apparatus of claim 1 , wherein each weighted AND gate comprises a plurality of branch segments connected in parallel, each branch segment comprising a switch that is selectively enabled via a respective bit of the multi-bit control signal.
9. The apparatus of claim 1 , wherein at least two weighted AND gates are configured to generate currents having different magnitudes.
10. The apparatus of claim 1 , further comprising a voltage controlled oscillator (VCO) connected to the output node, the VCO configured to adjust the local oscillator signal based on the local oscillator signal.
11. A method comprising:
generating a multi-bit control signal;
receiving, at four weighted AND gates, respective pairwise combinations of (i) a reference signal or its complement and (ii) a local oscillator signal or its complement;
sourcing and sinking current to an output node, wherein an amount of sourced or sunk current for each weighted AND gate is determined by a portion of the multi-bit control signal received at a respective control input; and
filtering the sourced and sunk currents on the output node to generate a local oscillator control signal.
12. The method of claim 11 , wherein the pairwise combinations of (i) the reference signal and the local oscillator signal and (ii) the complement of the reference signal and the complement of the local oscillator signal are received at first and second PMOS-based weighted AND gates of the four weighted AND gates, respectively.
13. The method of claim 11 , wherein the pairwise combinations of (i) the reference signal and the complement of the local oscillator signal and (ii) the complement of the reference signal and the local oscillator signal are received at first and second NMOS-based weighted AND gates of the four weighted AND gates, respectively.
14. The method of claim 11 , wherein filtering the sourced and sunk currents on the output node comprises charging and discharging a capacitor.
15. The method of claim 1 , further comprising receiving, at four additional weighted AND gates, respective pairwise combinations of (i) the reference signal or its complement and (ii) a second local oscillator signal or its complement; and
sourcing and sinking current to the output node using the four additional weighted AND gates.
16. The method of claim 15 , wherein the local oscillator control signal corresponds to a summation of currents sourced and sunk to the output node via the four weighted AND gates and the four additional weighted AND gates.
17. The method of claim 11 , wherein the portion of the multi-bit control signal received by each weighted AND gate is received at a resistor bank.
18. The method of claim 11 , wherein the amount of sourced or sunk current for each weighted AND gate is controlled by selectively enabling and disabling individual branch segments of a plurality of branch segments connected in parallel that constitute a given weighted AND gate.
19. The method of claim 11 , wherein current sourced to or sunk from the output node by at least two weighted AND gates have different magnitudes.
20. The method of claim 11 , further comprising providing the local oscillator signal to a voltage-controlled oscillator (VCO) connected to the output node to adjust the local oscillator signal based on the local oscillator control signal.