Granted Patent B2

US 12,336,264 · App. 17/844,971 · Granted Jun 17, 2025

Inventor: Hsih-Yang Chiu (Taoyuan, TW)

Assignee: NANYA TECHNOLOGY CORPORATION

H10D64/661H10D84/83H10D30/023H10D30/611H10D84/856H10D89/10

Abstract

Claims (45)

1. A semiconductor device, comprising:

a substrate;

a first gate electrode disposed on the substrate, wherein the first gate electrode is doped with a first dopant of a first conductive type;

a second gate electrode disposed on the substrate, wherein the second gate electrode is doped with a second dopant of a second conductive type different from the first conductive type; and

a first doped region, a second doped region, and a third doped region disposed in the substrate;

wherein the first gate electrode is located between the first doped region and the second doped region, wherein a distance between the first doped region and the second doped region is larger than a width of the first gate electrode, such that the first gate electrode is contactless with the first doped region and the second doped region;

wherein the second gate electrode is located between the second doped region and the third doped region, wherein a distance between the second doped region and the third doped region is larger than a width of the second gate electrode, such that the second gate electrode is contactless with the second doped region and the third doped region;

wherein the first doped region, the first gate electrode, the second doped region, the second gate electrode, and the third doped region are arranged in sequence along a first direction, wherein the first doped region, the first gate electrode, the second doped region, the second gate electrode, and the third doped region are spaced apart with each other along the first direction in a contactless manner;

wherein the first doped region, the first gate electrode, and the second doped region collectively define a first transistor;

wherein the second doped region, the second gate electrode, and the third doped region collectively define a second transistor;

wherein a first area of the first doped region is smaller than a second area of the second doped region in a top view, the second doped region is connected to ground, and the second doped region serves a shared source or a shared drain of the first transistor and the second transistor.

2. The semiconductor device of claim 1 , further comprising a first gate dielectric and a second gate dielectric disposed on the substrate, wherein the first gate electrode and the second gate electrode are respectively disposed on the first gate dielectric and the second gate dielectric, wherein a width of the first gate dielectric is equal to the width of first gate electrode, wherein a width of the second gate dielectric is equal to the width of second gate electrode, wherein the first gate electrode comprises a charge trapping material, wherein the first gate dielectric and the second gate dielectric are free from being doped with the first dopant and the second dopant.

3. The semiconductor device of claim 1 , wherein the first transistor has a first threshold voltage, and the second transistor has a second threshold voltage different from the first threshold voltage.

4. The semiconductor device of claim 3 , wherein the first transistor has a first channel region in the substrate between the first doped region and the second doped region, wherein the first channel region is free from being doped with the first dopant or the second dopant, wherein a length of the first channel region is larger than the width of the first gate electrode.

5. The semiconductor device of claim 3 , wherein the first transistor has a first channel region in the substrate between the first doped region and the second doped region, wherein the second transistor has a second channel region in the substrate between the second doped region and the third doped region, wherein at least one of the first dopant and the second dopant is free from being doped in both the first channel region and the second doped region, wherein a length of the first channel region is larger than the width of the first gate electrode, wherein a length of the second channel region is larger than the width of the second gate electrode.

6. A semiconductor device, comprising:

a substrate;

a first gate electrode disposed on the substrate, wherein the first gate electrode is doped with a first dopant of a first conductive type;

a second gate electrode disposed on the substrate, wherein the second gate electrode is doped with a second dopant of a second conductive type different from the first conductive type;

a first doped region, a second doped region, and a third doped region disposed in the substrate; and

a third gate electrode disposed on the substrate, wherein the third gate electrode has the second conductive type, the first gate electrode is aligned with the second gate electrode along a first direction, and the first gate electrode is aligned with the third gate electrode along a second direction different from the first direction;

wherein the first gate electrode is located between the first doped region and the second doped region, wherein a distance between the first doped region and the second doped region is larger than a width of the first gate electrode, such that the first gate electrode is contactless with the first doped region and the second doped region;

wherein the second gate electrode is located between the second doped region and the third doped region, wherein a distance between the second doped region and the third doped region is larger than a width of the second gate electrode, such that the second gate electrode is contactless with the second doped region and the third doped region;

wherein a distance between the first gate electrode and the second gate electrode along the first direction is different from a distance between the first gate electrode and its colinear second gate electrode along the second direction.

7. The semiconductor device of claim 6 , further comprising:

a fourth gate electrode disposed on the substrate, wherein the fourth gate electrode has the first conductive type, the fourth gate electrode is aligned with the third gate electrode along the first direction, and the fourth gate electrode is aligned with the second gate electrode along the second direction;

wherein a distance between the fourth gate electrode and the third gate electrode along the first direction is different from a distance between the fourth gate electrode and its colinear third gate electrode along the second direction.

8. The semiconductor device of claim 6 , further comprising:

a fourth gate electrode disposed on the substrate, wherein the fourth gate electrode has the second conductive type, the fourth gate electrode is aligned with the third gate electrode along the first direction, and the fourth gate electrode is aligned with the second gate electrode along the second direction;

wherein a distance between the fourth gate electrode and the third gate electrode along the first direction is different from a distance between the fourth gate electrode and its colinear third gate electrode along the second direction.

9. A semiconductor device, comprising:

a substrate;

a first gate electrode disposed on the substrate, wherein the first gate electrode is doped with a first dopant of a first conductive type;

a second gate electrode disposed on the substrate, wherein the second gate electrode is doped with a second dopant of a second conductive type different from the first conductive type;

a first doped region, a second doped region, and a third doped region disposed in the substrate; and

a third gate electrode disposed on the substrate, wherein the third gate electrode has the first conductive type, the first gate electrode is aligned with the second gate electrode along a first direction, and the first gate electrode is aligned with the third gate electrode along a second direction different from the first direction;

wherein the first gate electrode is located between the first doped region and the second doped region, wherein a distance between the first doped region and the second doped region is larger than a width of the first gate electrode, such that the first gate electrode is contactless with the first doped region and the second doped region;

wherein the second gate electrode is located between the second doped region and the third doped region, wherein a distance between the second doped region and the third doped region is larger than a width of the second gate electrode, such that the second gate electrode is contactless with the second doped region and the third doped region;

wherein a distance between the first gate electrode and the second gate electrode along the first direction is different from a distance between the first gate electrode and its colinear second gate electrode along the second direction.

10. The semiconductor device of claim 9 , further comprising:

a fourth gate electrode disposed on the substrate, wherein the fourth gate electrode has the first conductive type, the fourth gate electrode is aligned with the third gate electrode along the first direction, and the fourth gate electrode is aligned with the second gate electrode along the second direction;

wherein a distance between the fourth gate electrode and the third gate electrode along the first direction is different from a distance between the fourth gate electrode and its colinear third gate electrode along the second direction.

11. The semiconductor device of claim 9 , further comprising:

a fourth gate electrode disposed on the substrate, wherein the fourth gate electrode has the second conductive type, the fourth gate electrode is aligned with the third gate electrode along the first direction, and the fourth gate electrode is aligned with the second gate electrode along the second direction;

wherein a distance between the fourth gate electrode and the third gate electrode along the first direction is different from a distance between the fourth gate electrode and its colinear third gate electrode along the second direction.

Assignments (1)

Continuity (1)

References Cited (92)