IP Library › Granted Patent US 12,710,694
Granted Patent B2
US 12,710,694 · App. 18/814,426 · Granted Aug 18, 2026

Mask optimization for first layer that accounts for other layers

Inventors: Donald Oriordan (Sunnyvale, CA); Akira Fujimura (Saratoga, CA)
Assignee: D2S, INC.
G03F1/70G03F1/36G03F1/72G03F7/70441G03F7/705G06F30/398G03F7/70633G06F30/367G06F2119/18G06F2119/22
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Quick Facts
Patent No.
US 12,710,694
App. No.
18/814,426
Filed
Aug 23, 2024
Granted
Aug 18, 2026
Kind
B2
Examiner
TAT, BINH C
Art Unit
2851
USPC
716/53
Abstract

Some embodiments provide a method for optimizing a mask layout for producing masks that are used for manufacturing an integrated circuit (IC) comprising multiple layers of components. The method receives a mask layout including a set of mask images corresponding to a first layer of components of the IC that is adjacent to at least a second layer of components. The method generates a first wafer image including representations of IC components that are predicted to be manufactured for the first layer based on the received set of mask images corresponding to the first layer. Based on a positional relationship between at least one predicted IC component in the first wafer image and at least one predicted IC component in a second wafer image for the second layer, the method modifies at least one mask image in the set of mask images for the first layer.

Claims (42)

1 . A method for optimizing a mask layout for producing masks that are used for manufacturing an integrated circuit (IC) comprising multiple layers of components, the method comprising:

receiving a mask layout comprising a set of mask images corresponding to a first layer of components of the IC that is adjacent to at least a second layer of components;

generating a second-layer wafer image for the second layer of components based on a set of mask images corresponding to the second layer; and

iteratively:

generating a first-layer wafer image comprising representations of IC components that are predicted to be manufactured for the first layer based on a current set of mask images corresponding to the first layer;

and based on a positional relationship between at least one predicted IC component in the first-layer wafer image and at least one predicted IC component in the second-layer wafer image, modifying at least one mask image in the current set of mask images for the first layer to generate a modified set of mask images for the first layer,

wherein the second-layer wafer image is generated once and used each iteration for modifying the at least one mask image for the first layer.

2 . The method of claim 1 , wherein the set of mask images, when optimized, is used to fabricate a set of masks used for manufacturing the first layer of the IC.

3 . The method of claim 1 , wherein modifying the at least one mask image comprises:

identifying an objective function that accounts for (i) a difference between the first-layer wafer image and a target wafer image for the first layer and (ii) interaction of predicted IC components in the first-layer wafer image with predicted IC components in the second-layer wafer image; and

modifying the at least one mask image based on a calculated value for the objective function.

4 . The method of claim 1 , wherein:

the first layer is a metal layer and the second layer is a via layer;

the predicted IC component in the first-layer wafer image is a representation of an interconnect wire segment and the predicted IC component in the second-layer wafer image is a representation of a via that connects to the interconnect wire segment.

5 . The method of claim 1 , wherein:

the first layer is a via layer and the second layer is a metal layer;

the predicted IC component in the first-layer wafer image is a representation of a via and the predicted IC component in the second-layer wafer image is a representation of an interconnect wire segment that connects to the via.

6 . The method of claim 1 , wherein generating the first-layer wafer image comprises simulating a set of lithographic processes used to fabricate the first layer of the IC using a set of masks based on the set of mask images.

7 . The method of claim 1 , wherein generating the first-layer wafer image comprises providing the set of mask images as input to a machine-trained network that outputs the first-layer wafer image.

8 . The method of claim 1 , wherein generating the first-layer wafer image comprises:

rasterizing the set of mask images into a set of mask pixel images; and

generating the first-layer wafer image as a pixel image from the set of mask pixel images.

9 . The method of claim 1 , wherein modifying the at least one mask image comprises modifying a mask shape in one of the mask images that is used to produce the IC component in order to modify a shape of the produced IC component.

10 . A non-transitory machine-readable medium storing a program which when executed by at least one processing unit optimizes a mask layout for producing masks that are used for manufacturing an integrated circuit (IC) comprising multiple layers of components, the program comprising sets of instructions for:

receiving a mask layout comprising a set of mask images corresponding to a first layer of components of the IC that is adjacent to at least a second layer of components;

generating a second-layer wafer image for the second layer of components based on a set of mask images corresponding to the second layer; and

iteratively:

generating a first-layer wafer image comprising representations of IC components that are predicted to be manufactured for the first layer based on a current set of mask images corresponding to the first layer; and

based on a positional relationship between at least one predicted IC component in the first-layer wafer image and at least one predicted IC component in the second-layer wafer image, modifying at least one mask image in the current set of mask images for the first layer to generate a modified set of mask images for the first layer,

wherein the second-layer wafer image is generated once and used each iteration for modifying the at least one mask image for the first layer.

11 . The non-transitory machine-readable medium of claim 10 , wherein the set of mask images, when optimized, is used to fabricate a set of masks used for manufacturing the first layer of the IC.

12 . The non-transitory machine-readable medium of claim 10 , wherein the set of instructions for modifying the at least one mask image comprises sets of instructions for:

identifying an objective function that accounts for (i) a difference between the first-layer wafer image and a target wafer image for the first layer and (ii) interaction of predicted IC components in the first-layer wafer image with predicted IC components in the second-wafer wafer image; and

modifying the at least one mask image based on a calculated value for the objective function.

13 . The non-transitory machine-readable medium of claim 10 , wherein:

the first layer is a metal layer and the second layer is a via layer; and

the predicted IC component in the first-layer wafer image is a representation of an interconnect wire segment and the predicted IC component in the second-wafer wafer image is a representation of a via that connects to the interconnect wire segment.

14 . The non-transitory machine-readable medium of claim 10 , wherein:

the first layer is a via layer and the second layer is a metal layer; and

the predicted IC component in the first-layer wafer image is a representation of a via and the predicted IC component in the second-layer wafer image is a representation of an interconnect wire segment that connects to the via.

15 . The non-transitory machine-readable medium of claim 10 , wherein the set of instructions for generating the first-layer wafer image comprises a set of instructions for simulating a set of lithographic processes used to fabricate the first layer of the IC using a set of masks based on the set of mask images.

16 . The non-transitory machine-readable medium of claim 10 , wherein the set of instructions for generating the first-layer wafer image comprises a set of instructions for providing the set of mask images as input to a machine-trained network that outputs the first-layer wafer image.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 12, 2024
From: ORIORDAN, DONALD; FUJIMURA, AKIRA
To: D2S, INC.
Reel/Frame 069240/0194 →
Continuity (4)
Provisional Application 63679793 · Aug 6, 2024
Provisional Application 63608141 · Dec 8, 2023
Provisional Application 63534137 · Aug 23, 2023
Related Publication 20250068051A1 · Feb 27, 2025
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