Mask optimization accounting for more critical and less critical overlap regions
Some embodiments provide a method for optimizing a mask layout generated from a design layout of an IC. Based on an initial mask layout for a first layer, the method generates a simulated wafer image including shapes representing components of the first layer, including a first component that overlaps with a second component on a second layer. The method identifies a more critical first region and a less critical second region of a first shape of the first component that both overlap with a second shape of the second component. The more critical first region is more important to ensuring overlap of the first shape with the second shape. To improve overlap between the first and second shapes, the method uses different costs for the more critical first region and the less critical second region to modify the initial mask layout to produce a modified mask layout.
1 . A method for optimizing a mask layout generated from a design layout of an integrated circuit (IC), the method comprising:
based on an initial mask layout for a first layer of the design layout, generating a simulated wafer image comprising shapes representing IC components of the first layer, the first layer comprising a first IC component that overlaps with a second IC component on a second layer of the design layout;
identifying, in the simulated wafer image, a more critical first region and a less critical second region of a first shape of the first IC component that both overlap with a second shape of the second IC component, wherein the more critical first region is more important to ensuring overlap of the first IC component shape with the second IC component shape than the less critical second region; and
to improve overlap between the first and second shapes, using different costs for the more critical first region and the less critical second region to modify the initial mask layout to produce a modified mask layout to produce a mask to use to manufacture the IC.
2 . The method of claim 1 , wherein the first layer is a dielectric layer comprising a set of vias and the first-layer IC component is a particular via.
3 . The method of claim 2 , wherein the second-layer IC component is an interconnect wire segment in a metal layer that forms a connection with the particular via.
4 . The method of claim 3 , wherein:
the particular via overlaps with an end of the interconnect wire segment that traverses the metal layer in a particular direction;
the more critical first region of the particular via comprises sides of the particular via that, in the design layout, match sides of the interconnect wire segment traversing in the particular direction; and
the less critical second region of the particular via comprises sides of the particular via that, in the design layout, are perpendicular to the sides of the interconnect wire segment traversing in the particular direction.
5 . The method of claim 1 , wherein using different costs for the first region and the second region to modify the initial mask layout comprises identifying an objective function that accounts for (i) differences between the simulated wafer image and a target wafer image for the first layer and (ii) for each of a plurality of shapes representing IC components of the first layer, overlap of the first-layer IC component shape with a respective IC component shape in another layer of the design layout.
6 . The method of claim 5 , wherein:
each respective first-layer IC component shape of a set of the first-layer IC components has a respective more critical first region and a less critical second region that both overlap with the respective IC component shape in another layer; and
the respective more critical first regions and less critical second regions have different costs in the objective function.
7 . The method of claim 1 , wherein modifying the initial mask layout comprises modifying a mask shape in the mask layout that is used to produce the first-layer IC component during manufacturing of the IC.
8 . The method of claim 1 , wherein modifying the initial mask layout comprises adding at least one sub-resolution assist feature (SRAF) to or removing at least one SRAF from the mask layout.
9 . The method of claim 1 further comprising identifying a third region of a the first IC component shape that is not relevant to the overlap with the second IC component shape.
10 . The method of claim 9 , wherein a cost for the third region that is different than the costs for the first and second regions is used when modifying the initial mask layout.
11 . A non-transitory machine-readable medium storing a program which when executed by at least one processing unit optimizes for optimizing a mask layout generated from a design layout of an integrated circuit (IC), the program comprising sets of instructions for:
based on an initial mask layout for a first layer of the design layout, generating a simulated wafer image comprising shapes representing IC components of the first layer, the first layer comprising a first IC component that overlaps with a second IC component on a second layer of the design layout;
identifying, in the simulated wafer image, a more critical first region and a less critical second region of a first shape of the first IC component that both overlap with a second shape of the second IC component, wherein the more critical first region is more important to ensuring overlap of the first IC component shape with the second IC component shape than the less critical second region; and
to improve overlap between the first and second shapes, using different costs for the more critical first region and the less critical second region to modify the initial mask layout to produce a modified mask layout to produce a mask to use to manufacture the IC.
12 . The non-transitory machine-readable medium of claim 11 , wherein the first layer is a dielectric layer comprising a set of vias and the first-layer IC component is a particular via.
13 . The non-transitory machine-readable medium of claim 12 , wherein the second-layer IC component is an interconnect wire segment in a metal layer that forms a connection with the particular via.
14 . The non-transitory machine-readable medium of claim 13 , wherein:
the particular via overlaps with an end of the interconnect wire segment that traverses the metal layer in a particular direction;
the more critical first region of the particular via comprises sides of the particular via that, in the design layout, match sides of the interconnect wire segment traversing in the particular direction; and
the less critical second region of the particular via comprises sides of the particular via that, in the design layout, are perpendicular to the sides of the interconnect wire segment traversing in the particular direction.
15 . The non-transitory machine-readable medium of claim 11 , wherein the set of instructions for using different costs for the first region and the second region to modify the initial mask layout comprises a set of instructions for identifying an objective function that accounts for (i) differences between the simulated wafer image and a target wafer image for the first layer and (ii) for each of a plurality of shapes representing IC components of the first layer, overlap of the first-layer IC component shape with a respective IC component shape in another layer of the design layout.
16 . The non-transitory machine-readable medium of claim 15 , wherein:
each respective first-layer IC component shape of a set of the first-layer IC components has a respective more critical first region and a less critical second region that both overlap with the respective IC component shape in another layer; and
the respective more critical first regions and less critical second regions have different costs in the objective function.
17 . The non-transitory machine-readable medium of claim 11 , wherein the set of instructions for modifying the initial mask layout comprises a set of instructions for modifying a mask shape in the mask layout that is used to produce the first-layer IC component during manufacturing of the IC.
18 . The non-transitory machine-readable medium of claim 11 , wherein the set of instructions for modifying the initial mask layout comprises a set of instructions for adding at least one sub-resolution assist feature (SRAF) to or removing at least one SRAF from the mask layout.
19 . The non-transitory machine-readable medium of claim 11 , wherein the program further comprises a set of instructions for identifying a third region of a the first IC component shape that is not relevant to the overlap with the second IC component shape.
20 . The non-transitory machine-readable medium of claim 19 , wherein a cost for the third region that is different than the costs for the first and second regions is used when modifying the initial mask layout.