Apparatuses and methods for direct refresh management attack identification
Memory devices direct refresh management (DRFM) attack identification. A DRFM logic circuit receives DRFM aggressor address and compares it to a previous DRFM aggressor address. If there is not a match, then a DRFM operation is performed. If there is a match, then the DRFM operation may be skipped. This may prevent repeated DRFM operations from being performed on a same DRFM aggressor address.
1 . An apparatus comprising:
a direct refresh management (DRFM) logic circuit configured to latch a row address as a DRFM aggressor address responsive to receiving a sampling command, wherein the DRFM logic circuit is configured to provide an active skip signal if the DRFM aggressor address matches a previous DRFM aggressor address; and
a refresh state control circuit configured to perform a DRFM operation by performing a targeted refresh operation based on the DRFM aggressor address responsive to a DRFM flush command when the skip signal is inactive, or to skip performing the DRFM operation if the skip signal is active.
2 . The apparatus of claim 1 , wherein the DRFM logic circuit is configured to compare the DRFM aggressor address to a first previous DRFM aggressor address and a second previous DRFM aggressor address, and configured to provide the active skip signal if the DRFM aggressor address matches the first previous DRFM aggressor address or the second previous DRFM aggressor address.
3 . The apparatus of claim 1 , wherein the DRFM logic circuit is configured to store the DRFM aggressor address as the previous DRFM aggressor address responsive to performing the targeted refresh operation based on the DRFM aggressor address.
4 . The apparatus of claim 1 , further comprising:
an aggressor detector circuit configured to identify an address as an aggressor address;
an aggressor queue configured to store the identified aggressor address,
wherein the refresh state control circuit is configured to perform a targeted refresh operation based on the identified aggressor address in the aggressor queue responsive to a refresh management (RFM) signal.
5 . The apparatus of claim 4 , wherein the refresh state control circuit is configured to perform a targeted refresh operation based on the identified aggressor address in the aggressor queue responsive to skipping performing the DRFM operation.
6 . The apparatus of claim 1 , wherein the DRFM logic circuit comprises:
a first latch configured to store the DRFM aggressor address;
a second latch configured to store the previous DRFM aggressor address; and
a comparator circuit configured to compare the DRFM aggressor address in the first latch to the previous DRFM aggressor address in the second latch and provide a match signal if the DRFM aggressor address matches the previous DRFM aggressor address, wherein the active skip signal is provided based, in part, on the match signal.
7 . The apparatus of claim 6 , further comprising a DRFM control circuit configured to change a count value responsive to the match signal and to provide the active skip signal based on the changed count value.
8 . An apparatus comprising:
a first latch circuit configured to store a row address as a direct refresh management (DRFM) aggressor address responsive to a sampling signal;
a second latch circuit configured to store a previous DRFM aggressor address;
a comparator circuit configured to provide a match signal if the DRFM aggressor address matches the previous DRFM aggressor address; and
a DRFM control circuit configured to provide a DRFM skip signal based, in part, on the match signal, wherein a DRFM operation is skipped based, in part, on the DRFM skip signal.
9 . The apparatus of claim 8 , further comprising a refresh state control circuit configured to perform a DRFM operation responsive to a DRFM flush command when the DRFM skip signal is not provide and configured to skip performing the DRFM operation responsive to the DRFM flush command when the DRFM skip signal is provided.
10 . The apparatus of claim 9 , further comprising:
a refresh address generator configured to generate a refresh address based on the DRFM aggressor address responsive to the refresh state control circuit performing the DRFM operation; and
a row decoder configured to refresh one or more word lines based on the refresh address.
11 . The apparatus of claim 10 , further comprising an aggressor queue configured to store an aggressor address,
wherein the refresh state control circuit is configured to perform a targeted refresh operation responsive to skipping the DRFM operation, and
wherein the refresh address generator is configured to generate the refresh address based on the aggressor address in the aggressor queue responsive to the targeted refresh operation.
12 . The apparatus of claim 8 , wherein the DRFM control circuit is configured to change a count value responsive to the match signal, and configured to not provide the DRFM skip signal and reset the count value responsive to the count value reaching a threshold value.
13 . The apparatus of claim 8 , further comprising:
a third latch circuit configured to store a second previous DRFM address; and
a second comparator circuit configured to provide a second match signal if the DRFM aggressor address matches the second previous DRFM address,
wherein the DRFM control circuit is configured to provide the DRFM skip signal based, in part, on the match signal and the second match signal.
14 . The apparatus of claim 8 , wherein the DRFM control circuit is configured to store the DRFM aggressor address from the first latch as the previous DRFM aggressor address in the second latch responsive to a DRFM flush signal when the DRFM skip signal is not provided.
15 . A method comprising:
receiving a direct refresh management (DRFM) aggressor address as part of a DRFM operation;
comparing the DRFM aggressor address to a previous DRFM aggressor address; and
skipping the DRFM operation if the DRFM address matches the previous DRFM address.
16 . The method of claim 15 , further comprising refreshing one or more word lines based on the DRFM aggressor address as part of the DRFM operation if the DRFM operation is not skipped.
17 . The method of claim 15 , further comprising:
counting a number of times the DRFM operation is skipped; and
performing the DRFM operation when the count reaches a threshold even if the DRFM address matches the previous DRFM address.
18 . The method of claim 15 , further comprising storing the DRFM aggressor address in a latch as the previous DRFM aggressor if the DRFM operation is not skipped.
19 . The method of claim 15 , further comprising:
comparing the DRFM aggressor address to a second previous DRFM aggressor address; and
skipping the DRFM operation if the DRFM address matches the first or the second previous DRFM aggressor address.
20 . The method of claim 15 , further comprising:
identifying an aggressor address and storing the identified aggressor address in an aggressor queue; and
performing a targeted refresh operation on the aggressor address from the aggressor queue responsive to skipping the DRFM operation.