Patent Assignment
Reel/Frame 013776/0139
Assignment of Assignor's Interest
Recorded: 2003-02-19
Received: 2003-02-26
Pages: 2
Assignor
NEC CORPORATION
Executed: 2002-11-01
Assignee
NEC ELECTRONICS CORPORATION
1753 SHIMONUMABE, NAKAHARA-KU, KAWASAKI, KANAGAWA 211-8668, JPX, JAPAN
Covered Properties
(56)
Low Power Logic Gate
Application:
10/347,723 →
Thermal Characterization Chip
Application:
10/345,637 →
Co-Deposited Films with Nano-Columnar Structures and Formation Process
Application:
10/341,651 →
Nanowire Filament
Application:
10/326,708 →
Electronic Device Sealed Under Vacuum Containing a Getter and Method of Operation
Application:
10/328,261 →
System for and Method of Assessing Chip Acceptability and Increasing Yield
Application:
10/309,967 →
Method of Forming a Through-Substrate Interconnect
Application:
10/286,060 →
Phase shift mask and fabrication method therefor
Application:
10/283,807 →
System and Method for Designing Dynamic Circuits in a Soi Process
Application:
10/282,342 →
Semiconductor manufacturing apparatus and method, semiconductor device and electronic device
Application:
10/281,567 →
Clock Pulse Width Control Circuit
Application:
10/280,472 →
Method of Using Clock Cycle-Time in Determining Loop Schedules During Circuit Design
Application:
10/266,826 →
Method for Designing Minimal Cost, Timing Correct Hardware During Circuit Synthesis
Application:
10/266,831 →
System and Method for Reducing Wire Delay or Congestion During Synthesis of Hardware Solvers
Application:
10/266,719 →
Methods and Apparatus for Digital Circuit Design Generation
Application:
10/266,856 →
System for and Method of Clock Cycle-Time Analysis Using Mode-Slicing Mechanism
Application:
10/266,830 →
Emitter Device with Focusing Columns
Application:
10/264,599 →
Emission Device and Method for Forming
Application:
10/262,808 →
Nanometer-Scale Semiconductor Devices and Method of Making
Application:
10/256,984 →
Large Line Conductive Pads for Interconnection of Stackable Circuitry
Application:
10/245,897 →
Embossed Mask Lithography
Application:
10/244,862 →
Technique for Testing Processor Interrupt Logic
Application:
10/241,453 →
Method and Apparatus for Improving Testability of I/O Driver/Receivers
Application:
10/238,570 →
Semiconductor Device Capable of Internally Generating Bias Changing Signal
Application:
10/225,865 →
Method and Apparatus for Simplifying a Circutt Model
Application:
10/213,960 →
Method of Forming a Through-Substrate Interconnect
Application:
10/208,163 →
Method of Forming a Through-Substrate Interconnect
Application:
10/208,363 →
Printed circuit board having plating conductive layer with bumps and its manufacturing method
Application:
10/205,323 →
Verifying Proximity of Ground Vias to Signal Vias in an Integrated Circuit
Application:
10/199,668 →
Emitter with Dielectric Layer Having Implanted Conducting Centers
Application:
10/197,722 →
Layout Design Process and System for Providing Bypass Capacitance and Compliant Density in an Integrated Circuit
Application:
10/197,346 →
Stacked Chip-Size Package Type Semiconductor Device Capable of Being Decreased in Size
Application:
10/190,655 →
System and Method for Measuring Fault Coverage in an Integrated Circuit
Application:
10/184,496 →
Semiconductor Storage Device and Production Method Thereof
Application:
10/183,701 →
Systems and Methods for Generating an Artwork Representation According to a Circuit Fabrication Process
Application:
10/174,674 →
Transistor with Means for Providing a Non-Silicon-Based Emitter
Application:
10/172,213 →
Wire Bonding Apparatus with Spurious Vibration Suppressing Structure
Application:
10/164,069 →
Diode-And-Fuse Memory Elements for a Write-Once Memory Comprising an Anisotropic Semiconductor Sheet
Application:
10/160,802 →
Data Bus with Separate Matched Line Impedances and Method of Matching Line Impedances
Application:
10/157,496 →
Address Structure and Methods for Multiple Arrays of Data Storage Memory
Application:
10/145,337 →
Semiconductor Automation Markup Language Based Gem/Secs Development Application
Application:
10/138,455 →
Semiconductor device formed with metal wiring on a wafer by chemical mechanical polishing, and method of manufacturing the same
Application:
10/135,487 →
Method of Fabricating a Sub-Lithographic Sized Via
Application:
10/133,605 →
Method of Fabricating Sub-Lithographic Sized Line and Space Patterns for Nano-Imprinting Lithography
Application:
10/133,772 →
Emitter with Filled Zeolite Emission Layer
Application:
10/126,426 →
Mems Device Having a Flexure with Integral Electrostatic Actuator
Application:
10/125,098 →
Test Method for Characterizing Currents Associated with Powered Components in an Electronic System
Application:
10/121,356 →
Pressure Sensor with Two Membranes Forming a Capacitor
Application:
10/120,944 →
Method and Apparatus for Identifying Switching Race Conditions in a Circuit Design
Application:
10/114,545 →
Electrical Device and Method of Making
Application:
10/114,392 →
Method of Optimizing High Performance Cmos Integrated Circuit Designs for Power Consumption and Speed Through Genetic Optimization
Application:
10/098,136 →
Method of Modeling the Crossover Current Component in Submicron Cmos Integrated Circuits Designs
Application:
10/098,112 →
Method of Optimizing High Performance Cmos Integrated Circuit Designs for Power Consumption and Speed
Application:
10/098,111 →
Method of Optimizing High Performance Cmos Integrated Circuit Designs for Power Consumption and Speed Using Global and Greedy Optimizations in Combination
Application:
10/098,110 →
Distributed translation network for parallel job execution using registry scheme
Application:
10/094,676 →
Emission Layer Formed by Rapid Thermal Formation Process
Application:
10/085,866 →