Patent Assignment
Reel/Frame 033261/0088
Change of Name
Recorded: 2014-07-01
Pages: 10
Assignor
INTERSIL CORPORATION
Executed: 2001-05-23
Assignee
INTERSIL COMMUNICATIONS, INC.
1001 MURPHY RANCH ROAD, MILPITAS, CALIFORNIA, 95035
Covered Properties
(186)
Telephone Subscriber Line Circuit, Components and Methods
Patent:
5,745,563 →
Application:
07/840,547 →
Bicmos Devices
Patent:
5,856,695 →
Application:
07/917,635 →
Semicondcuctor Device with Increased Maximum Terminal Voltage Voltage
Patent:
6,008,512 →
Application:
08/053,243 →
Method of Making Intergrated Circuit Structure with Narrow Line Widths
Patent:
5,639,688 →
Application:
08/066,355 →
Low Voltage Rf Amplifier and Mixer with Single Bias Block and Method
Patent:
5,809,410 →
Application:
08/090,617 →
Process for Manufacturing a Multi-Port Adhesive Dispensing Tool
Patent:
5,423,889 →
Application:
08/265,355 →
Current Follower with Zero Input Impedance
Patent:
5,614,867 →
Application:
08/266,567 →
High Speed a/D Converter and Slew Controlled Pulse Detector
Patent:
5,808,489 →
Application:
08/269,470 →
Graphical Display Discriminant Factor Indicator for Anomaly Identification in Semiconductor Manufacture Batch Process
Patent:
5,450,326 →
Application:
08/271,292 →
Cmos Integrated Circuit Architecture Incorporating Deep Implanted Emitter Region to Form Auxiliary Bipolar Transistor
Patent:
6,350,640 →
Application:
08/276,290 →
Method of Making Contact Regions for Narrow Trenches in Semiconductor Devices
Patent:
5,622,890 →
Application:
08/279,027 →
Video Scaling Method and Device
Patent:
5,574,572 →
Application:
08/301,622 →
Programmable Element in Barrier Metal Device
Patent:
5,648,678 →
Application:
08/310,280 →
Structure and Tailoring Effective Resistivity of a Sipos Layer by Patterning and Control of Dopant Introduction
Patent:
5,637,908 →
Application:
08/314,489 →
Sigma-Delta Analog to Digital Converter with Three Point Calibration Apparatus and Method
Patent:
5,598,157 →
Application:
08/331,015 →
Method for Making Ohmic Contact to Lightly Doped Islands from a Silicide Buried Layer and Applications
Patent:
5,643,821 →
Application:
08/336,768 →
Differential Longitudinal Amplifier for a Subscriber Line Interface Circuit
Patent:
5,649,009 →
Application:
08/340,342 →
Switch Controller and Method
Patent:
5,636,274 →
Application:
08/372,118 →
Current Mode Ring Trip Detector
Patent:
5,671,272 →
Application:
08/380,409 →
Circuit and Method for Loopback Test and on-Hook Transmission Integrated in a Telephone Subscriber Line Interface Circuit
Patent:
5,659,570 →
Application:
08/380,411 →
Filter with Reduced Element Ratings and Method
Patent:
5,572,162 →
Application:
08/380,412 →
Method and Circuit for Failsafe Switch-Hook Detection During Fault in a Telephone System
Patent:
5,812,658 →
Application:
08/380,413 →
Configuration Independent Auto-Biasing of Bipolar Transistor
Patent:
5,625,566 →
Application:
08/382,346 →
High Voltage, Junction Isolation Semiconductor Device Haivng Dual Conductivity Tape Buried Regions and Its Process of Manufacture
Patent:
5,567,978 →
Application:
08/383,261 →
Simulation of Noise Behavior of Non-Linear Circuit
Patent:
5,682,336 →
Application:
08/386,785 →
Multiple Use Timer and Method for Pulse Width Generation, Echo Failure Detection, and Receive Pulse Width Measurement
Patent:
5,661,736 →
Application:
08/395,591 →
Crc Generation and Detection Method
Patent:
5,724,370 →
Application:
08/395,814 →
Zero Phase Error Switched-Capacitor Phase Locked Loop Filter
Patent:
5,659,269 →
Application:
08/402,381 →
Process for Doping Two Levels of a Double Poly Bipolar Transistor After Formation of Second Poly Layer
Patent:
5,614,422 →
Application:
08/405,660 →
Digital Component Testing Apparatus and Method
Patent:
5,644,309 →
Application:
08/419,610 →
Method of Forming Dummy Island Capacitor
Patent:
5,602,052 →
Application:
08/427,231 →
Multi-Channel Sigma-Delta a/D Converters with Improved Throughput
Patent:
5,617,090 →
Application:
08/438,251 →
Bimos Driver Circuit and Method
Patent:
5,576,654 →
Application:
08/441,726 →
Method of Forming P-Type Islands Over P-Type Buried Layer
Patent:
5,633,180 →
Application:
08/456,727 →
Integrated Circuit with Coaxial Isolation and Method
Patent:
5,814,889 →
Application:
08/461,037 →
Surface Mountable Integrated Circuit with Conductive Vias
Patent:
5,608,264 →
Application:
08/461,643 →
Method of Bonding Wafers Having Vias Including Conductive Material
Patent:
5,646,067 →
Application:
08/461,951 →
Method of Fabrication of Surface Mountable Integrated Circuits
Patent:
5,618,752 →
Application:
08/462,171 →
System for Interconnecting Stacked Integrated Circuits
Patent:
5,682,062 →
Application:
08/462,876 →
Integrated Circuit with Edge Connections and Method
Patent:
5,668,409 →
Application:
08/463,388 →
High Efficiency Quasi-Vertical Dmos in Cmos or Bicmos Process
Patent:
5,777,362 →
Application:
08/474,559 →
Defect Control in Formation of Dielectrically Isolated Semiconductor Device Regions
Patent:
5,750,432 →
Application:
08/481,115 →
Local Oxidation Process for High Field Threshold Applications
Patent:
5,580,816 →
Application:
08/481,116 →
High Efficiency Power Mos Switch
Patent:
5,689,129 →
Application:
08/483,691 →
Pilot Transistor for Quasi-Vertical Dmos Device
Patent:
5,684,305 →
Application:
08/483,692 →
Battery Operated Inverter Circuit for Capacitive Loads Such as Electroluminescent Lamps
Patent:
5,557,175 →
Application:
08/490,016 →
Electroluminescent Lamp Driver System
Patent:
5,539,707 →
Application:
08/490,952 →
Sign Bit Integrator and Method
Patent:
5,617,473 →
Application:
08/493,454 →
Level Shifter with Improved Rejection of Voltage Variations
Patent:
5,627,489 →
Application:
08/493,824 →
Offset Adjustment for Fully Differential Amplifiers
Patent:
5,736,885 →
Application:
08/494,395 →
Digital Decoder and Method for Decoding Composite Video Signals
Patent:
5,621,477 →
Application:
08/496,868 →
Multistandard Decoder for Video Signals and Video Signal Decoding Method
Patent:
5,621,478 →
Application:
08/497,008 →
Scr Inductor Transient Clamp
Patent:
5,546,038 →
Application:
08/497,124 →
Sample Rate Converter and Sample Rate Conversion Method
Patent:
5,619,270 →
Application:
08/497,181 →
Method of Making Non-Uniformly Nitrided Gate Oxide
Patent:
5,650,344 →
Application:
08/503,048 →
Fast Recovery Temperature Compensated Reference Source
Patent:
5,621,307 →
Application:
08/505,671 →
Automatic Fault Monitoring System and Motor Control System Incorporating Same
Patent:
5,642,247 →
Application:
08/505,695 →
Inverted Bjt Current Sources/Sinks in Rf Circuits and Methods
Patent:
5,654,662 →
Application:
08/506,978 →
Device and Method for Enhancing Thermal and High Frequency Performance of Integrated Circuit Packages
Patent:
5,581,444 →
Application:
08/507,192 →
Arrangement and Method for Improving Room-Temperature Testability of Cmos Integrated Circuits Optimized for Cryogenic Temperature Operation
Patent:
5,696,452 →
Application:
08/512,323 →
Wide Common Mode Range Comparator and Method
Patent:
5,614,852 →
Application:
08/512,417 →
Integrated Circuit with Diamond Insulator
Patent:
5,650,639 →
Application:
08/513,950 →
Statistically Based Current Generator Circuit
Patent:
5,701,097 →
Application:
08/515,435 →
Method of Manufacturing a Programmable Hybrid Balance Network
Patent:
5,610,093 →
Application:
08/527,548 →
Device and Method for Improving Corrosion Resistance and Etch Tool Integrity in Dry Metal Etching
Patent:
5,830,279 →
Application:
08/536,257 →
Sampled Data-Biasing of Continuous Time Integrated Circuit
Patent:
5,621,355 →
Application:
08/537,051 →
Testing Circuit and Method for a Codec Hybrid Balance Network
Patent:
5,717,736 →
Application:
08/552,379 →
Magnetic Boats
Patent:
5,669,599 →
Application:
08/552,711 →
Common Mode Stabilizing Circuit and Method
Patent:
5,668,468 →
Application:
08/584,366 →
Method and Apparatus for Radiation Hardened Isolation
Patent:
5,670,413 →
Application:
08/586,556 →
Composition, and Method for Using Same, for Etching Metallic Alloys from a Substrate
Patent:
5,587,103 →
Application:
08/587,692 →
Method for Providing a Silicon and Diamond Substrate Having a Carbon to Silicon Transistion Layer and Apparatus Thereof
Patent:
5,782,975 →
Application:
08/587,953 →
Differential Interpolating Switched Capacitor Filter and Method
Patent:
5,680,072 →
Application:
08/590,940 →
Electrostatic Discharge Protection Device
Patent:
5,883,414 →
Application:
08/596,079 →
Interpolating Digital to Analog Converter Architecture for Improved Spurious Signal Suppression
Patent:
5,798,724 →
Application:
08/601,401 →
Method to Improve the Peak-Current Limit in a Slope-Compensated, Current-Mode Dc/Dc Converter, and Circuit Therefor
Patent:
5,717,322 →
Application:
08/602,287 →
Current-Controlled Carrier Tracking Filter for Improved Spurious Signal Suppression
Patent:
5,953,379 →
Application:
08/606,958 →
Phase Meter and Method of Providing a Voltage Indicative of a Phase Difference
Patent:
5,831,423 →
Application:
08/608,728 →
Digitally Programmable Differential Attenuator with Tracking Common Mode Reference
Patent:
5,742,204 →
Application:
08/608,812 →
Circuit for Driving an Electroluminescent Lamp
Patent:
5,677,599 →
Application:
08/613,381 →
Carrier Buffer Having Current-Controlled Tracking Filter for Spurious Signal Suppression
Patent:
5,736,903 →
Application:
08/637,140 →
Process Forming Trench Isolation Device
Patent:
5,933,746 →
Application:
08/637,937 →
Method of Making a Reference Current Generator
Patent:
5,686,822 →
Application:
08/640,108 →
Planarization Method by Use of Particle Dispersion and Subsequent Thermal Flow
Patent:
5,837,603 →
Application:
08/643,295 →
Semiconductor Device with Doped Semiconductor and Dielectric Trench Sidewall Layers
Patent:
5,856,700 →
Application:
08/646,471 →
Integrated Circuit with an Air Bridge Having a Lid
Patent:
5,825,092 →
Application:
08/650,688 →
Pre-Bond Cavity Air Bridge
Patent:
5,949,144 →
Application:
08/650,762 →
Semiconductor Packaging Apparatus
Patent:
5,965,933 →
Application:
08/654,316 →
Radiation Hardened Dielectric for Eeprom
Patent:
5,808,353 →
Application:
08/666,258 →
Clock-Controlled Precision Monostable Circuit
Patent:
5,920,219 →
Application:
08/669,066 →
Up-Conversion Mechanism Employing Side Libe-Selective Pre- Distortion Felter and Frequency Repleca-Selecting Bandpass Filter Respectively Enstalled Upstream and Downstream of Digital- to-Analog Converter
Patent:
5,930,301 →
Application:
08/671,025 →
Double Diffused Mos Device and Method
Patent:
5,817,564 →
Application:
08/671,157 →
Integrated Circuit Containing Devices Dielectrically Isolated and Junction Isolated from a Substrate
Patent:
5,841,169 →
Application:
08/671,243 →
Charge-Based Frequency Locked Loop and Method
Patent:
5,841,324 →
Application:
08/671,781 →
High Voltage Protection Circuits
Patent:
5,663,860 →
Application:
08/673,396 →
Electrically Variable R/C Network and Method
Patent:
5,767,757 →
Application:
08/687,995 →
Lid Wafer Bond Packaging and Micromachining
Patent:
5,798,557 →
Application:
08/705,536 →
P-Collector H.V. Pmos Switch Vt Adjusted Source/Drain
Patent:
5,770,880 →
Application:
08/707,271 →
Two Trim Current Source and Method for a Digital-to-Analog Converter
Patent:
5,923,209 →
Application:
08/707,380 →
Integrated Circuit Analog-to-Digital Converter and Associated Calibration Method and Apparatus
Patent:
5,771,012 →
Application:
08/712,027 →
Digital- to- Analog Converter Having Enhanced Current Steering and Associated Method
Patent:
5,790,060 →
Application:
08/714,019 →
Integrated Circuit Having Enhanced Transient Voltage Protection and Associated Methods
Patent:
5,708,549 →
Application:
08/726,183 →
Surface Mount Die by Handle Replacement
Patent:
5,807,783 →
Application:
08/726,659 →
Analog-To-Digital Converter and Method of Fabrication
Patent:
5,994,755 →
Application:
08/739,898 →
Deep Trench Etch on Bonded Silicon Wafer
Patent:
5,914,280 →
Application:
08/771,944 →
Re-Sampling Circuit and Modulator Using Same
Patent:
5,764,113 →
Application:
08/781,334 →
Interpolator Using a Plurality of Polynomial Equations and Associated Methods
Patent:
5,949,695 →
Application:
08/781,736 →
Pivot Sample Block Cross-Section Tool
Patent:
5,830,048 →
Application:
08/798,039 →
Integrated Circuit with Thin Film Resistors and a Method for Co-Patterning Thin Film Resistors with Different Compositions
Patent:
5,976,944 →
Application:
08/799,793 →
Dc-To-Dc Converter Having Enhanced Control Features and Associated Methods
Patent:
5,793,193 →
Application:
08/799,959 →
Dc-To-Dc Converter Having Fast Over-Current Detection and Associated Methods
Patent:
5,821,740 →
Application:
08/800,420 →
Dc-To-Dc Converter Having Charge Pump and Associated Methods
Patent:
5,808,883 →
Application:
08/800,421 →
Reduce Width, Differentially Doped Vertical Jfet Device
Patent:
5,945,699 →
Application:
08/855,385 →
Integrated Circuit Chip Structure for Improved Packaging
Patent:
5,900,643 →
Application:
08/858,845 →
Dynamic Regulator for a Dc-to-Dc Power Converter and Related Methods
Patent:
5,926,384 →
Application:
08/883,624 →
Method and Apparatus for Calibrating Integrated Circuit Analog-to-Digital Converters
Patent:
5,861,826 →
Application:
08/885,273 →
Processor Controlled Analog-to-Digital Converter Circuit
Patent:
5,892,472 →
Application:
08/885,274 →
Method for Forming Complementary Wells and Self-Aligned Trench with a Single Mask
Patent:
5,956,583 →
Application:
08/885,707 →
Multilayer Microtip Probe and Method
Patent:
5,892,223 →
Application:
08/885,897 →
Hermetic Thin Oack Semiconductor Device
Patent:
6,157,076 →
Application:
08/885,923 →
Digital-To-Analog Converter Including Current Cell Matrix with Enhanced Linearity and Associated Methods
Patent:
5,949,362 →
Application:
08/916,569 →
Electrical System with Small Signal Suppression Circuitry
Patent:
6,060,913 →
Application:
08/918,307 →
Comparator with Small Signal Suppression Circuitry
Patent:
5,892,375 →
Application:
08/918,345 →
Constant Slew Rate Amplifier
Patent:
6,040,707 →
Application:
08/929,734 →
Knock Sensor System for Detecting and Responding to a Disconnect Condition
Patent:
5,942,677 →
Application:
08/931,340 →
Schmitt Trigger-Configured Esd Protection Circuit
Patent:
5,978,192 →
Application:
08/964,672 →
Low Distortion Current Feedback Amplifier with Dynamic Biasing
Patent:
5,977,829 →
Application:
08/972,887 →
Monolithic Class D Amplifier
Patent:
5,973,368 →
Application:
08/973,769 →
Multiple Output Dc-to-Dc Converter Having Enhanced Noise Margin and Related Methods
Patent:
6,058,030 →
Application:
08/974,862 →
Rf Communications System Operable in the Presence of a Repetitive Interference Source and Related Methods
Patent:
6,006,071 →
Application:
09/006,071 →
Adjustable Phase Clock Circuit Using Same and Related Methods
Patent:
5,990,713 →
Application:
09/019,241 →
Optimum Placement of Bypass Capacitors in a Network for Improving Electro-Magnetic Interference Response
Patent:
6,091,274 →
Application:
09/024,099 →
Network for Improving Electro-Magnetice Interference Response
Patent:
5,920,224 →
Application:
09/024,203 →
Ring Generator
Patent:
6,167,131 →
Application:
09/027,257 →
Igbt Gate Drive Circuit with Short Circuit Protection
Patent:
6,275,093 →
Application:
09/030,871 →
Sample-And-Hold Circuit Having Reduced Subthreshold Conduction Effects and Related Methods
Patent:
6,069,502 →
Application:
09/055,528 →
Sample-And-Hold Circuit Having Reduced Parasitic Diode Effects and Related Methods
Patent:
6,002,277 →
Application:
09/055,561 →
Sample-And-Hold Circuit Having Reduced Amplifier Offset Effects and Related Methods
Patent:
6,016,067 →
Application:
09/055,562 →
Devices with Patterned Wells and Method for Forming Same
Sc-2 Based Pre-Thermal Treatment Wafer Cleaning Process
Patent:
5,932,022 →
Application:
09/064,029 →
Battery Switching Subscriber Loop Interface Circuit
Patent:
6,233,335 →
Application:
09/079,304 →
Defect Gettering by Induced Stress
Patent:
5,929,508 →
Application:
09/082,892 →
Decapsulating Method and Apparatus for Integrated Circuit Packages
Patent:
6,054,012 →
Application:
09/106,622 →
Method of Creating a Solderable Metal Layer on Glass or Ceramic
Patent:
6,159,663 →
Application:
09/107,475 →
Linear Voltage Regulator Compatible with Bipolar and Mosfet Pass Devices and Associated Methods
Patent:
6,005,303 →
Application:
09/108,059 →
Electrostatic Discharge Locating Apparatus and Method
Patent:
6,064,340 →
Application:
09/108,963 →
Flat Power Rack
Patent:
6,057,612 →
Application:
09/109,268 →
Parasitic Current Barriers
Patent:
6,278,186 →
Application:
09/139,932 →
Programmable Subscriber Loop Interface Circuit and Method
Patent:
6,665,398 →
Application:
09/145,182 →
Analog-To-Digital Converter Having Enhanced Accuracy Gain Stage, and Associated Devices and Methods
Patent:
6,107,950 →
Application:
09/148,955 →
Digital-To-Analog Converter Including Current Sources Operable in a Predetermined Sequence and Associated Methods
Patent:
6,118,398 →
Application:
09/149,154 →
Device Containing Sample Preparation Sites for Transmission Electron Microscopic Analysis and Processes of Formation and Use
Patent:
6,140,652 →
Application:
09/150,429 →
Integrated Circuit Air Bridge Structures and Methods of Fabricating Same
Patent:
6,211,056 →
Application:
09/199,292 →
Apparatus and Method for Testing Subscriber Loop Interface Circuits
Patent:
6,519,322 →
Application:
09/208,457 →
Complementary Multiplexer with Low Disabled-Output Capacitance, and Method
Patent:
6,114,896 →
Application:
09/247,510 →
Method for Forming a Bonded Substrate Containing a Planar Intrinsic Gettering Zone and Substrate Formed by Said Method
Patent:
6,255,195 →
Application:
09/255,231 →
Laser Decapsulation Method
Patent:
6,335,208 →
Application:
09/307,896 →
Method of Forming an Integrated Resistive Contacts with Mobility Spoiling Ions Including High Resistivity Contacts and Low Resistivity Silicide Contacts
Patent:
6,403,472 →
Application:
09/339,274 →
Brushless Multipass Silicon Wafer Cleaning Process for Post Chemical Mechanical Polishing Using Immersion
Patent:
6,526,995 →
Application:
09/342,948 →
Method of Manufacturing a Plated Electronic Termination
Edge Termination for Silicon Power Devices
Patent:
6,242,784 →
Application:
09/344,868 →
Method for Making a Diffused Back-Side Layer on a Bonded-Wafer with a Thick Bond Oxide
Patent:
6,362,075 →
Application:
09/345,261 →
Low Temperature Coefficient Resistor (Tcrl)
Patent:
6,351,021 →
Application:
09/345,929 →
Use of Barrier Refractive or Anti-Reflective Layer to Improve Laser Trim Characteristics of Thin Film Resistors
Patent:
6,259,151 →
Application:
09/358,266 →
Line Circuit Apparatus for Supplying Power to a Telephone Set in Telec
Patent:
6,137,189 →
Application:
09/365,238 →
Co-Patterning Thin-Film Resistors of Different Compositions with a Conductive Hard Mask and Method for Same
Patent:
6,441,447 →
Application:
09/367,325 →
Apparatus and Method for Measuring Loop Impedance
Patent:
6,434,232 →
Application:
09/378,962 →
Backwards Drivable Mos Output Driver
Patent:
6,362,665 →
Application:
09/442,291 →
Breakdown Improvement Method and Structure for Lateral Dmos Device
Patent:
6,614,088 →
Application:
09/506,711 →
Subsampling Digitizer-Based Frequency Synthesizer
Accessing Main Atx Outputs Without Monitoring All Outputs
Patent:
6,882,942 →
Application:
09/552,117 →
Floating gate circuit for backwards driven MOS output driver
Patent:
6,351,158 →
Application:
09/569,894 →
Oscillator Having Reduced Sensitivity to Supply Voltage Changes
Patent:
6,552,622 →
Application:
09/639,407 →
Transconductance Amplifier Circuit
Patent:
6,411,163 →
Application:
09/639,408 →
Cascadable, high efficiency charge pump circuit and related methods
Patent:
6,249,446 →
Application:
09/645,070 →
Controlled Switching Mechanism for Accomplishing Soft Polarity Reversal, Ring-Trip Filtering, and Line Voltage Measurements in a Subscriber Line Interface Circuit Using Common Capacitor
Patent:
6,862,352 →
Application:
09/686,247 →
Precision Loop Voltage Detector for Subscriber Line Interface Circuit Applications
Patent:
6,469,519 →
Application:
09/686,324 →
Mechanism for Preventing Clipping of Pulse Metering Signals in Telephone Line Card Channels
Patent:
6,829,353 →
Application:
09/686,504 →
Precision, Low-Power Current-Sense Transmission Channel for Subscriber Line Interface Circuit, Programmable with Single Ended Impedances and Capable of Exhibiting a Voltage Sense Response
Patent:
6,873,703 →
Application:
09/686,505 →
Precision, low-power transimpedance circuit with differential current sense inputs and single ended voltage output
Patent:
6,292,033 →
Application:
09/686,506 →
Mechanism for Minimizing Undesirable Effects of Parasitic Components in Integrated Circuits
Patent:
6,396,331 →
Application:
09/686,514 →
Mechanism for Generating Precision User-Programmable Parameters in Analog Integrated Circuit
Patent:
6,407,621 →
Application:
09/686,515 →
Mechanism for Measuring Resistance of Telephone Subscriber Line and Generating Measurement as Pulse Width of Periodic Waveform
Patent:
6,504,927 →
Application:
09/686,517 →
Transistor base current error correction scheme for low overhead voltage applications
Patent:
6,344,776 →
Application:
09/686,634 →
Biasing Arrangement for Optimizing Dc Feed Characteristics for Subscriber Line Interface Circuit
Patent:
6,829,354 →
Application:
09/686,926 →
Dc to Dc Converter Method and Circuitry
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.