IP Library › Assignment 036017/0001

Patent Assignment

Reel/Frame 036017/0001

Assignment of Assignor's Interest

Recorded: 2015-06-26 Pages: 152

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Assignor

SPANSION, LLC

Executed: 2015-06-01

Assignee

CYPRESS SEMICONDUCTOR CORPORATION

198 CHAMPION COURT, SAN JOSE, CALIFORNIA, 95134

Covered Properties (26)

Method of Fabricating a High Dielectric Constant Interpolysilicon Dielectric Structure for a Low Voltage Non-Volatile Memory

Patent: 6,020,238 →

Application: 08/978,107 →

Method of Fabricating an Oxynitride-Capped High Dielectric Constant Interpolysilicon Dielectric Structure for a Low Voltage Non-Volatile Memory.

Patent: 6,025,228 →

Application: 08/978,398 →

Method for Forming a Low Barrier Height Oxide Layer on a Silicon Substrate

Patent: 6,017,786 →

Application: 08/982,186 →

Elimination of Poly Stringers with Straight Poly Profile

Patent: 6,046,085 →

Application: 08/986,951 →

A Charging and Discharging Device for an Electronic Apparatus, and an Electronic Apparatus Including the Same, Utilizing a Charging Device Providing a Constant Charging Current

Patent: 6,008,629 →

Application: 08/989,517 →

Method for Fully Planarized Conductive Line for a Stack Gate

Patent: 6,027,998 →

Application: 08/992,536 →

Methods and Arrangements for Forming a Floating Gate in Non-Volatile Memory Semiconductor Devices

Patent: 6,034,394 →

Application: 08/992,950 →

Methods for Forming a Control Gate Apparatus in Non-Volatile Memory Semiconductor Devices

Patent: 6,063,662 →

Application: 08/993,409 →

Method and System for Using a Spacer to Offset Implant Damage and Reduce Lateral Diffusion in Flash Memory Devices

Patent: 6,025,240 →

Application: 08/993,600 →

Split Voltage for Nand Flash

Patent: 6,005,804 →

Application: 08/993,634 →

Method and System for Gate Stack Reoxidation Control

Patent: 6,015,736 →

Application: 08/993,787 →

Low Power Prescaler for a Pll Circuit

Patent: 6,031,425 →

Application: 09/014,250 →

Elimination of Oxynitride (Ono) Etch Residue and Polysilicon Stringers Through Isolation of Floating Gates on Adjacent Bitlines by Polysilicon Oxidation

Patent: 6,043,120 →

Application: 09/033,723 →

Elimination of Oxynitride (Ono) Etch Residue and Polysilicon Stringers Through Isolation of Floating Gates on Adjacent Bitlines by Polysilicon Oxidation

Patent: 6,030,868 →

Application: 09/033,916 →

A Semiconductor Device Having a Reduced Height Floating Gate

Patent: 6,034,395 →

Application: 09/092,352 →

Semiconductor Device Including a Boost Circuit

Patent: 6,060,914 →

Application: 09/131,778 →

Method for Sensing State of Erasure of a Flash Electrically Erasable Programmable Read-Only Memory (Eeprom)

Patent: 6,011,721 →

Application: 09/132,347 →

Method for Tightening Erase Threshold Voltage Distribution in Flash Electrically Erasable Programmable Read-Only Memory (Eeprom)

Patent: 6,052,310 →

Application: 09/132,981 →

Stacked Gate Structure for Flash Memory Application

Patent: 6,060,741 →

Application: 09/154,072 →

Metal Oxide Stack for Flash Memory Application

Patent: 6,011,289 →

Application: 09/154,073 →

Method of Making Flexibly Partitioned Metal Line Segments for a Simultaneous Operation Flash Memory Device with a Flexible Bank Partition Architecture

Patent: 6,033,955 →

Application: 09/159,023 →

Memory Address Decoding Circuit for a Simultaneous Operation Flash Memory Device with a Flexible Bank Partition Architecture

Patent: 6,005,803 →

Application: 09/159,342 →

Flash Memory Device Having High Permittivity Stacked Dielectric and Fabrication Thereof

Patent: 6,048,766 →

Application: 09/172,410 →

Three-Dimensional Non-Volatile Memory

Patent: 6,043,122 →

Application: 09/334,393 →

Operational Approach for the Suppression of Bi-Directional Tunnel Oxide Stress of a Flash Cell