Patent Assignment
Reel/Frame 019069/0040
Assignment of Assignor's Interest
Recorded: 2007-03-27
Pages: 6
Assignor
SPANSION INC.
Executed: 2007-01-31
Assignee
SPANSION LLC
915 DEGUIGNE DRIVE, P.O. BOX 3453, MAIL STOP 250, SUNNYVALE, CALIFORNIA, 94088-3453
Covered Properties
(35)
Method for Forming a Low Barrier Height Oxide Layer on a Silicon Substrate
Patent:
6,017,786 →
Application:
08/982,186 →
Method of Eliminating Poly Stringer in a Memory Device
Patent:
6,001,688 →
Application:
08/986,860 →
Elimination of Poly Stringers with Straight Poly Profile
Patent:
6,046,085 →
Application:
08/986,951 →
Reduction of Ono Fence During Self-Aligned Etch to Eliminate Poly Stringers
Patent:
5,933,729 →
Application:
08/986,953 →
Semiconductor Device with Multiple Contact Sizes
Patent:
5,994,780 →
Application:
08/991,052 →
Interlevel Dielectric Thickness Monitor for Complex Semiconductor Chips
Patent:
6,072,191 →
Application:
08/991,299 →
Methods and Arrangements for Forming a Tapered Floating Gate in Non-Volatile Memory Semiconductor Devices
Patent:
5,973,353 →
Application:
08/992,951 →
Novel Nand Type Core Cell Structure for a High Density Flash Memory Device Having a Unique Select Gate Transistor Configuration
Patent:
6,667,511 →
Application:
08/993,368 →
A Low Dielectric Constant Material and Method of Application to Isolate Conductive Lines
Patent:
6,166,439 →
Application:
09/000,739 →
Method for Preventing P1 Punchthrough
Patent:
5,972,749 →
Application:
09/002,783 →
Methods and Arrangements for Reducing Stress and Preventing Cracking in a Silicide Layer
Patent:
6,211,074 →
Application:
09/076,584 →
Methods for Removing Silicide Residue in a Semiconductor Device
Patent:
6,159,794 →
Application:
09/076,662 →
Methods for Preventing Silicide Residue Formation in a Semiconductor Device
Patent:
6,074,956 →
Application:
09/076,663 →
Method of Soft-Landing Gate Etching to Prevent Gate Oxide Damage
Patent:
5,948,703 →
Application:
09/092,924 →
Method for Etching Layers on a Semiconductor Wafer in a Single Etching Chamber
Patent:
6,159,860 →
Application:
09/118,375 →
Method for Etching Memory Gate Stack Using Thin Resist Layer
Patent:
5,977,601 →
Application:
09/118,377 →
Method and Structure of Etching a Memory Cell Polisilicon Gate Layer Using Resist Mask and Etched Silicon Oxynitride
Patent:
6,110,779 →
Application:
09/118,382 →
Scalable and Reliable Integrated Circuit Inter-Level Dielectric
Patent:
6,124,640 →
Application:
09/144,506 →
Reduction of Silicon Oxynitride Film Delamination in Integrated Circuit Inter-Level Dielectrics
Patent:
6,133,619 →
Application:
09/144,521 →
Stacked Gate Structure for Flash Memory Application
Patent:
6,060,741 →
Application:
09/154,072 →
Metal Oxide Stack for Flash Memory Application
Patent:
6,011,289 →
Application:
09/154,073 →
Semiconductor Device Containing P-Hdp Interdielectric Layer
Patent:
6,080,639 →
Application:
09/199,265 →
Semiconductor Devices with Reduced Control Gate Dimensions
Patent:
6,515,328 →
Application:
09/244,429 →
Method and Apparatus for Preventing P1 Punchthrough
Patent:
6,066,873 →
Application:
09/271,330 →
Method for Trimming a Photoresist Pattern Line for Memory Gate Etching
Patent:
6,372,651 →
Application:
09/286,464 →
Light Floating Gate Doping to Improve Tunnel Oxide Reliability
Patent:
6,232,630 →
Application:
09/348,583 →
Thin Floating Gate and Conductive Select Gate in Situ Doped Amorphous Silicon Material for Nand Type Flash Memory Device Applications
Patent:
6,235,586 →
Application:
09/352,801 →
Semiconductor Device with Multiple Contact Sizes
Patent:
6,211,058 →
Application:
09/353,781 →
Methods and Arrangements for Forming a Single Interpoly Dielectric Layer in a Semiconductor Device
Patent:
6,433,383 →
Application:
09/357,333 →
Method for Etching Memory Gate Stack Using Thin Resist Layer
Patent:
6,383,939 →
Application:
09/375,504 →
A Method of Forming a Nand -Type Flash Memory Device H Aving a Non-Stacked Select Gate Transistor Structure
Patent:
6,316,293 →
Application:
09/531,749 →
Method of High Density Plasma Metal Etching
Patent:
6,534,411 →
Application:
09/548,616 →
Interlevel dielectric thickness monitor for complex semiconductor chips
Patent:
6,350,627 →
Application:
09/548,741 →
Method and structure of etching a memory cell polysilicon gate layer using resist mask and etched silicon oxynitride
Patent:
6,452,225 →
Application:
09/617,820 →
Method of Degassing Low K Dielectric for Metal Deposition
Patent:
6,436,850 →
Application:
09/652,132 →
Related Assignments
(17)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Sep 16, 2003
From: JAIN, MOHIT KUMAR
To: APPLIED MATERIALS, INC.
Reel/Frame 014499/0046 →
Assignment of Assignor's Interest
Mar 19, 2007
From: ADVANCED MICRO DEVICES, INC.
To: SPANSION INC.
Reel/Frame 019028/0629 →
Security Agreement
Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
Assignment of Assignor's Interest
Sep 27, 2013
From: YANG, WENGE; SHEN, LEWIS
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 031301/0071 →
Release of Security Interest
Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
Assignment of Assignor's Interest
Jun 26, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036017/0001 →
Assignment of Assignor's Interest
Jun 26, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036017/0473 →
Assignment of Assignor's Interest
Jun 26, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036017/0625 →
Assignment of Assignor's Interest
Jun 26, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036019/0156 →
Assignment of Assignor's Interest
Jun 26, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036019/0518 →
Assignment of Assignor's Interest
Jun 29, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036031/0355 →
Assignment of Assignor's Interest
Jun 29, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036027/0730 →
Assignment of Assignor's Interest
Jun 29, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036025/0453 →
Assignment of Assignor's Interest
Jun 29, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036034/0415 →
Assignment of Assignor's Interest
Jun 29, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036030/0196 →
Partial Release of Security Interest in Patents
Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
Assignment of Assignor's Interest
Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →