Method and apparatus for improved high-speed adaptive equalization
View Patent ↗A method and apparatus for improved high-speed adaptive equalization that may operate effectively even in systems experiencing severe interference by using one or more error generators and taking multiple samples across a bit interval. Advantageously, a preferred embodiment of the current invention may be deployed in a clockless configuration. Preferably, one or more controllable analog filters may be controlled by one or more microprocessors used to assess the error data from the error generators and to calculate the appropriate coefficients for the filters according to one or more error minimization algorithms. Preferably, the steps of sampling, assessment, calculation and coefficient setting may be done iteratively to converge to an optimum set of filter values and/or respond dynamically to signals with time-varying noise and interference characteristics.
1. An improved high-speed adaptive equalizer device comprising:
one or more controllable analog filters comprising:
one or more data signal inputs for receiving one or more data signals;
one or more control signal inputs for receiving one or more control signals; and
one or more outputs for carrying filtered data signals as output signals; and
one or more error generators for assessing the performance of one or more of said controllable analog filters according to one or more error functions coupled to one or more of said analog filters, the one or more error generators comprising:
one or more inputs for receiving one or more of said filtered data signals from a controllable analog filter, wherein a weighting function is applied to at least one of said filtered data signals received from said controllable analog filter to emphasize a first portion of said filtered data signal over a second portion of said filtered data signal, said first portion corresponding to a middle point of a signal eye pattern representing signal amplitude versus time and said second portion corresponding to a zero crossing point of said signal eye pattern; and
one or more outputs for carrying error generator output data signals.
2. The improved high-speed adaptive equalizer device of claim 1 further comprising one or more processing modules for processing said error generator output data signals creating processed data signals.
3. An improved high-speed adaptive equalizer device comprising:
one or more controllable analog filters including:
one or more data signal inputs for receiving one or more data signals;
one or more control signal inputs for receiving one or more control signals; and
one or more outputs for carrying filtered data signals as output signals; and
one or more error generators for assessing the performance of one or more of said controllable analog filters according to one or more error functions coupled to one or more of said analog filters including:
one or more inputs for receiving one or more of said filtered data signals from a controllable analog filter, wherein a weighting function is applied to at least one of said filtered data signals received from said controllable analog filter to emphasize a first portion of said filtered data signal over a second portion of said filtered data signal, said first portion corresponding to a middle point of a signal eye pattern representing signal amplitude versus time and said second portion corresponding to a zero crossing point of said signal eye pattern; and
one or more outputs for carrying error generator output data signals; and
one or more processing modules for processing said error generator output data signals creating processed data signals, wherein one or more of said processing modules comprise one or more error acquisition blocks for applying one or more acquisition filters to one or more of said error generator output data signals thereby creating one or more processed signals coupled to one or more of said error generators comprising:
one or more inputs for receiving said error generator output data signals; and
one or more outputs for carrying processed data signals.
4. The improved high-speed adaptive equalizer device of claim 3 wherein one or more of said acquisition filters comprise an anti-aliasing filter, a noise reduction filter, a low pass filter or an integrator.
5. The improved high-speed adaptive equalizer device of claim 1 further comprising one or more equalizer controllers for controlling one or more of said controllable analog filters according to one or more algorithms comprising:
one or more inputs for receiving equalizer controller input data signals; and
one or more outputs for carrying said control signals coupled to one or more of said control signal inputs.
6. The improved high-speed adaptive equalizer device of claim 5 wherein said equalizer controller input data signals comprise processed data signals or error generator output data signals.
7. The improved high-speed adaptive equalizer device of claim 1 wherein said controllable analog filter device comprises a digital, analog or hybrid device.
8. The improved high-speed adaptive equalizer device of claim 5 wherein one or more of said algorithms comprise a quasi-Newton, steepest descent or multivariate minimization algorithm.
9. The improved high-speed adaptive equalizer device of claim 5 wherein one or more of said algorithms may be added, updated, activated, decommissioned or deleted.
10. The improved high-speed adaptive equalizer device of claim 1 wherein one or more of said error functions may be added, updated, activated, decommissioned or deleted.
11. The improved high-speed adaptive equalizer device of claim 1 wherein said analog filter comprises one or more transversal filters, lattice filters, linear filters or non-linear filters.
12. The improved high-speed adaptive equalizer device of claim 1 wherein one or more of said data signal inputs comprise analog input, sampled analog input or digital input.
13. The improved high-speed adaptive equalizer device of claim 1 wherein one or more of said control signal inputs comprise analog input or digital input.
14. The improved high-speed adaptive equalizer device of claim 5 wherein said equalizer controller comprises one or more processing units, microprocessors, software modules, firmware modules or digital devices.
15. The improved high-speed adaptive equalizer device of claim 5 wherein said equalizer controller further comprises one or more external data outputs.
16. The improved high-speed adaptive equalizer device of claim 5 wherein said (equalizer controller further comprises one or more external control signal outputs.
17. The improved high-speed adaptive equalizer device of claim 5 wherein said equalizer controller further comprises one or more external data inputs.
18. The improved high-speed adaptive equalizer device of claim 17 wherein said equalizer controller further comprises one or more external control signal inputs.
19. The improved high-speed adaptive equalizer device of claim 1 wherein one or more of said controllable analog filters further comprises one or more external data signal outputs.
20. The improved high-speed adaptive equalizer device of claim 1 wherein one or more of said error generators further comprises one or more external data signal outputs.
21. The improved high-speed adaptive equalizer device of claim 1 wherein one or more of said error generators comprises one or more eye monitors.
22. The improved high-speed adaptive equalizer device of claim 1 wherein one or more of said error generators comprises a clock or clock recovery system.
23. The improved high-speed adaptive equalizer device of claim 1 wherein one or more of said error generators is coupled to a clock or clock recovery system.
24. The improved high-speed adaptive equalizer device of claim 1 wherein one or more of said error generators comprises one or more weighting function modules.
25. The improved high-speed adaptive equalizer device of claim 1 further comprising one or more modules comprising a capacity reporting module, a device status module, a link monitor or a monitoring module.
26. The improved high-speed adaptive equalizer device of claim 1 further comprising one or more modules comprising a joint optimization module, a chromatic dispersion module, a receiver gain module, a sampling phase module, a decision threshold level module or a DC offset module.
27. A method for improved high-speed adaptive equalization, said method comprising:
receiving one or more data inputs at one or more controllable analog filters;
filtering said one or more data inputs according to filter coefficients to create one or more filtered data signals;
receiving said filtered data signals at one or more error generators;
applying a weighting function to at least one of said filtered data signals to emphasize a first portion of said filtered data signal over a second portion of said filtered data signal, said first portion corresponding to a middle point of a signal eye pattern representing signal amplitude versus time and said second portion corresponding to a zero crossing point of said signal eye pattern; and
assessing the performance of one or more of said controllable analog filters according to one or more error functions creating one or more error generator output data signals.
28. The method of claim 27 further comprising providing one or more external data output signals after said filtering.
29. The method of claim 27 wherein said assessing the performance of one or more of said controllable analog filters further comprises applying a function to said filtered data signals comprising a normalization function or level shift function.
30. The method of claim 27 wherein said assessing the performance of one or more of said controllable analog filters further comprises applying one or more weighting functions to said error generator output data signals.
31. The method of claim 27 further comprising processing said error generator Output signals creating processed data signals.
32. A method for improved high-speed adaptive equalization, said method comprising:
receiving one or more data inputs at one or more controllable analog filters;
filtering said one or more data inputs according to filter coefficients to create one or more filtered data signals;
receiving said filtered data signals at one or more error generators;
applying a weighting function at least one of said filtered data signals to emphasize a first portion of said filtered data signal over a second portion of said filtered data signal, said first portion corresponding to a middle point of a signal eye pattern representing signal amplitude versus time and said second portion corresponding to a zero crossing point of said signal eye pattern;
assessing the performance of one or more of said controllable analog filters according to one or more error functions creating one or more error generator output data signals; and
processing said error generator output signals creating processed data signals,
wherein said processing said error generator output signals comprises:
receiving said error generator output data signals at an error acquisition module; and
filtering said error generator output data signals according to one or more acquisition filters.
33. The method of claim 32 wherein said filtering said error generator output data signals according to one or more acquisition filters comprises processing said error generator output data signals with a filter comprising an anti-aliasing filter, a noise reduction filter, a low pass filter or an integrator.
34. The method of claim 32 further comprising digitizing said error generator output data signals.
35. The method of claim 27 further comprising:
receiving equalizer controller input data signals at an equalizer controller;
computing a new set of filter coefficients according to one or more error minimization algorithms; and
controlling one or more of said controllable analog filters by adjusting said filter coefficients to said new set of filter coefficients.
36. The method of claim 35 wherein said equalizer controller input data signals comprise processed data signals or error generator output data signals.
37. The method of claim 35 further comprising executing joint optimization with respect to one or more external devices.
38. The method of claim 35 further comprising assessing capacity, device status or link monitor status based on said filter coefficients.
39. The method of claim 38 further comprising reporting said capacity, device status or link monitor status based on said filter coefficients.
40. The method of claim 27 further comprising operating iteratively.
41. The method of claim 27 further comprising initializing one or more of said controllable analog filters to an initial setting comprising a set of said filter coefficients based on a pass-through mode, stored values or external input.
42. A system for improved optical networking comprising an improved high-speed adaptive equalizer device comprising:
one or more controllable analog filters comprising:
one or more data signal inputs for receiving one or more data signals;
one or more control signal inputs for receiving one or more control signals; and
one or more outputs for carrying filtered data signals as output signals; and
one or more error generators for assessing the performance of one or more of said controllable analog filters according to one or more error functions coupled to one or more of said analog filters, the one or more error generators comprising:
one or more inputs for receiving one or more of said filtered data signals from a controllable analog filter, wherein a weighting function is applied to at least one of said filtered data signals received from said controllable analog filter to emphasize a first portion of said filtered data signal over a second portion of said filtered data signal, said first portion corresponding to a middle point of a signal eye pattern representing signal amplitude versus time and said second portion corresponding to a zero crossing point of said signal eye pattern; and
one or more outputs for carrying error generator output data signals.
43. The system of claim 42 wherein said improved high-speed adaptive equalizer further comprises one or more processing modules for processing said error generator output data signals creating processed data signals.
44. A system for improved optical networking comprising:
an improved high-speed adaptive equalizer device including:
one or more controllable analog filters comprising:
one or more data signal inputs for receiving one or more data signals;
one or more control signal inputs for receiving one or more control signals; and
one or more outputs for carrying filtered data signals as output signals; and
one or more error generators for assessing the performance of one or more of said controllable analog filters according to one or more error functions coupled to one or more of said analog filters including:
one or more inputs for receiving one or more of said filtered data signals from a controllable analog filter, wherein a weighting function is applied to at least one of said filtered data signals received from said controllable analog filter to emphasize a first portion of said filtered data signal over a second portion of said filtered data signal, said first portion corresponding to a middle point of a signal eye pattern representing signal amplitude versus time and said second portion corresponding to a zero crossing point of said signal eye pattern; and
one or more outputs for carrying error generator output data signals,
wherein said improved high-speed adaptive equalizer further comprises one or more processing modules for processing said error generator output data signals creating processed data signals, and
wherein one or more of said processing modules comprise one or more error acquisition blocks for applying one or more acquisition filters to one or more of said error generator output data signals thereby creating one or more processed signals coupled to one or more of said error generators comprising:
one or more inputs for receiving said error generator output data signals; and
one or more outputs for carrying processed data signals.
45. The system of claim 44 wherein one or more of said acquisition filters comprise an anti-aliasing filter, a noise reduction filter, a low pass filter or an integrator.
46. The system of claim 42 wherein said improved high-speed adaptive equalizer further comprises one or more equalizer controllers for controlling one or more of said controllable analog filters according to one or more algorithms comprising:
one or more inputs for receiving equalizer controller input data signals; and
one or more outputs for carrying said control signals coupled to one or more of said control signal inputs.
47. The system of claim 46 wherein said equalizer controller input data signals comprise processed data signals or error generator output data signals.
48. The system of claim 42 wherein said controllable analog filter device comprises a digital, analog or hybrid device.
49. The system of claim 46 wherein one or more of said algorithms comprise a quasi-Newton, steepest descent or multivariate minimization algorithm.
50. The system of claim 46 wherein one or more of said algorithms may be added, updated, activated, decommissioned or deleted.
51. The system of claim 42 wherein one or more of said error functions may be added, updated, activated, decommissioned or deleted.
52. The system of claim 42 wherein said analog filter comprises one or more transversal filters, lattice filters, linear filters or non-linear filters.
53. The system of claim 42 wherein one or more of said data signal inputs comprise analog input, sampled analog input or digital input.
54. The system of claim 42 wherein one or more of said control signal inputs comprise analog input or digital input.
55. The system of claim 46 wherein said equalizer controller comprises one or more processing units, microprocessors, software modules, firmware modules or digital devices.
56. The system of claim 46 wherein said equalizer controller further comprises one or more external data outputs.
57. The system of claim 46 wherein said equalizer controller further comprises one or more external control signal outputs.
58. The system of claim 57 wherein said equalizer controller further comprises one or more external data inputs.
59. The system of claim 42 wherein one or more of said controllable analog filters further comprises one or more external data signal outputs.
60. The system of claim 42 wherein one or more of said error generators further comprises one or more external data signal outputs.
61. The system of claim 42 wherein one or more of said error generators comprises one or more eye monitors.
62. The system of claim 42 wherein one or more of said error generators comprises a clock or clock recovery system.
63. The system of claim 42 wherein one or more of said error generators is coupled to a clock or clock recovery system.
64. The system of claim 42 wherein one or more of said error generators comprises one or more weighting function modules.
65. The system of claim 42 wherein said improved high-speed adaptive equalizer device further comprises one or more modules comprising a capacity reporting module, a device status module, a link monitor or a monitoring module.
66. The system of claim 42 wherein said improved high-speed adaptive equalizer device further comprises one or more modules comprising a joint optimization module, a chromatic dispersion module, a receiver gain module, a sampling phase module, a decision threshold level module or a DC offset module.