Interposer substrate and semiconductor package
A semiconductor package includes a first semiconductor package including a first substrate and a lower semiconductor chip mounted on the first substrate, a second semiconductor package stacked on the first semiconductor package and including a second substrate and an upper semiconductor chip mounted on the second substrate, and an interposer substrate interposed between the first semiconductor package and the second semiconductor package and having a recess recessed from a lower surface facing the lower semiconductor chip, wherein the interposer substrate includes a dummy wiring layer disposed to be adjacent to the recess, in a region overlapped with the lower semiconductor chip, and no electrical signal is applied to the dummy wiring layer.
1. A semiconductor package comprising:
a first semiconductor package including a first substrate and a lower semiconductor chip mounted on the first substrate;
a second semiconductor package stacked on the first semiconductor package and including a second substrate and an upper semiconductor chip mounted on the second substrate; and
an interposer substrate interposed between the first semiconductor package and the second semiconductor package and having a recess recessed from a lower surface facing the lower semiconductor chip,
wherein the interposer substrate includes a dummy wiring layer disposed to be adjacent to the recess in a region overlapped with the lower semiconductor chip, and
wherein the dummy wiring layer is electrically floating.
2. The semiconductor package of claim 1 , wherein the interposer substrate further includes a lower insulating layer covering a lower surface of the dummy wiring layer.
3. The semiconductor package of claim 1 , wherein at least a portion of the dummy wiring layer is exposed to the recess.
4. The semiconductor package of claim 3 , wherein at least a portion of the dummy wiring layer is in contact with an upper surface of the lower semiconductor chip.
5. The semiconductor package of claim 1 , wherein the dummy wiring layer has a single pattern or includes a plurality of patterned patterns.
6. The semiconductor package of claim 1 , wherein the interposer substrate further includes protrusions spaced apart from each other on a lower surface forming the recess.
7. The semiconductor package of claim 6 , wherein at least portions of the protrusions are in contact with an upper surface of the lower semiconductor chip.
8. The semiconductor package of claim 1 , wherein the interposer substrate includes:
a core insulating layer having an embedded wiring layer;
a lower insulating layer disposed below the core insulating layer and having the recess; and
an interconnecting wiring layer disposed on a lower surface of the lower insulating layer, on a periphery of the recess.
9. The semiconductor package of claim 8 , wherein the dummy wiring layer is disposed within the lower insulating layer.
10. The semiconductor package of claim 8 , wherein the core insulating layer and the lower insulating layer include different materials.
11. The semiconductor package of claim 10 , wherein the core insulating layer includes glass fiber and the lower insulating layer consists of a resin and an inorganic filler.
12. The semiconductor package of claim 8 , further comprising:
connecting terminals disposed between the interconnecting wiring layer and the first substrate.
13. The semiconductor package of claim 1 , wherein the interposer substrate further includes a peripheral wiring layer disposed on a perimeter of the recess, on the same vertical level as the dummy wiring layer.
14. The semiconductor package of claim 1 , wherein the first substrate has a cavity corresponding to a region in which the lower semiconductor chip is mounted.
15. A semiconductor package comprising:
a substrate;
a semiconductor chip mounted on the substrate;
an interposer substrate disposed on the semiconductor chip and electrically connected to the substrate; and
connecting terminals connecting the substrate and the interposer substrate,
wherein the interposer substrate includes:
a core insulating layer having an embedded wiring layer;
a lower insulating layer disposed below the core insulating layer and having a recess recessed from a lower surface facing the semiconductor chip;
a dummy wiring layer disposed between the embedded wiring layer and the semiconductor chip above the recess, the dummy wiring layer being electrically floating; and
an interconnecting wiring layer disposed on a lower surface of the lower insulating layer and connected to the connecting terminals, on a periphery of the recess.
16. The semiconductor package of claim 15 , wherein the dummy wiring layer is disposed on a lower surface of the core insulating layer.
17. The semiconductor package of claim 15 , wherein the dummy wiring layer is disposed within the lower insulating layer.
18. The semiconductor package of claim 15 , wherein the lower insulating layer exposes at least a portion of the dummy wiring layer.
19. An interposer substrate comprising:
a core insulating layer having an embedded wiring layer;
a lower insulating layer disposed below the core insulating layer and having a recess recessed from a lower surface at the center of the lower surface; and
a dummy wiring layer disposed on a lower surface of the core insulating layer above the recess,
wherein the dummy wiring layer is electrically floating.
20. The interposer substrate of claim 19 , further comprising:
an interconnecting wiring layer disposed on a lower surface of the lower insulating layer, on a perimeter of the recess; and
connecting terminals disposed on a lower surface of the interconnecting wiring layer.