Apparatuses, systems, and methods for per row error scrub information registers
Apparatuses, systems, and methods for per row error correct and scrub (pRECS) registers. A mode register may include a pRECS enable register, to enable a pRECS mode. When the prECS mode is enabled, pRECS information associated with each row may be collected which reflects a number of codewords stored along that row which were determined to include an error during error correct and scrub (ECS) operations. The memory may store the pRECS information in the memory array, for example, each row may store the pRECS information associated with that row. A pRECS address register may specify a location in the memory array to store the pRECS information.
1 . An apparatus, comprising:
a memory array comprising a first plurality of memory cells at the intersection of a first word line and a plurality of bit lines and a second plurality of memory cells at the intersection of a second word line and the plurality of bit lines, wherein a first plurality of codewords are stored in at least some of the first plurality of memory cells and a second plurality of codewords are stored in at least some of the second plurality of memory cells;
a mode register configured to store a per-row error correct and scrub (ECS) count enable signal; and
ECS logic configured to:
count a first number of the first plurality of codewords along the first word line which contain an error when the per-row ECS count enable signal is active;
count a second number of the second plurality of codewords along the second word line which contain an error when the per-row ECS count enable signal is active;
collect other ECS information, the other ECS information including a third number of the first plurality of codewords and the second plurality of codewords which include errors regardless of whether the per-row ECS count enable signal is active or not, the other ECS information comprising at least one of an error count (EC) count value or an errors per row count (EpRC) count value; and
store the first number in the memory array.
2 . The apparatus of claim 1 , wherein:
a first portion of the first plurality of memory cells is used to store data;
a second portion of the first plurality of memory cells is used to store metadata associated with the data;
a third portion of the first plurality of memory cells is used neither for data or metadata; and
the ECS logic is configured to store the first number in the third portion.
3 . The apparatus of claim 2 , wherein the mode register also includes a per-row ECS address which specifies selected ones of the first plurality of memory cells used to store the first number.
4 . The apparatus of claim 3 , wherein the per-row ECS address specifies a column address signal associated with selected ones of the plurality of bit lines.
5 . The apparatus of claim 3 , further comprising a fuse array configured to store the per-row ECS address which is loaded into the mode register.
6 . The apparatus of claim 1 , wherein the ECS logic is configured to store the first number and the second number in the memory array.
7 . The apparatus of claim 1 , wherein the EC count value represents total codewords or rows with at least one codeword error, and wherein the EpRC count value represents a maximum number of codewords with errors which are located on a single row address and the row address of the row with the maximum number of errors.
8 . An apparatus, comprising:
a memory array comprising a first plurality of memory cells at the intersection of a first word line and a plurality of bit lines and a second plurality of memory cells at the intersection of a second word line and the plurality of bit lines, wherein a first plurality of codewords is stored in at least some of the first plurality of memory cells and a second plurality of codewords is stored in at least some of the second plurality of memory cells;
a mode register configured to store a per-row error correct and scrub (ECS) count enable signal; and
ECS logic configured to:
count a first number of the first plurality of codewords along the first word line which contain an error when the per-row ECS count enable signal is active;
count a second number of the second plurality of codewords along the second word line which contain an error when the per-row ECS count enable signal is active; and
store the first number in one or more stranded columns of the memory array, wherein the one or more stranded columns are configured as non-addressable memory in at least a mode of the apparatus.
9 . The apparatus of claim 8 , wherein:
a first portion of the plurality of memory cells is used to store data;
a second portion of the plurality of memory cells is used to store metadata associated with the data;
a third portion of the plurality of memory cells is used neither for data or metadata; and
the ECS logic is configured to store the first number in the third portion.
10 . The apparatus of claim 8 , wherein the ECS logic is configured to collect other ECS information regardless of whether the per-row ECS count enable signal is active or not, the other ECS information comprising at least one of an error count (EC) count or an errors per row count (EpRC) count.
11 . An apparatus, comprising:
a memory array comprising a first plurality of memory cells at the intersection of a first word line and a plurality of bit lines and a second plurality of memory cells at the intersection of a second word line and the plurality of bit lines, wherein a first plurality of codewords is stored in at least some of the first plurality of memory cells and a second plurality of codewords is stored in at least some of the second plurality of memory cells;
a mode register configured to store a per-row error correct and scrub (ECS) count enable signal; and
ECS logic configured to:
count a first number of the first plurality of codewords along the first word line which contain an error when the per-row ECS count enable signal is active;
count a second number of the second plurality of codewords along the second word line which contain an error when the per-row ECS count enable signal is active; and
store the first number in the memory array, wherein:
a first portion of the plurality of memory cells is used to store data;
a second portion of the plurality of memory cells is used to store metadata associated with the data;
a third portion of the plurality of memory cells is used neither for data or metadata; and
the ECS logic is configured to store the first number in the third portion, wherein the mode register is configured to store a per-row ECS address that specifies selected ones of the plurality of memory cells used to store the first number.
12 . The apparatus of claim 11 , wherein the per-row ECS address specifies a column address signal associated with selected ones of the plurality of bit lines.
13 . The apparatus of claim 11 , further comprising a fuse array configured to store the per-row ECS address which is loaded into the mode register.
14 . An apparatus, comprising:
a memory array comprising a first plurality of memory cells at the intersection of a first word line and a plurality of bit lines and a second plurality of memory cells at the intersection of a second word line and the plurality of bit lines, wherein a first plurality of codewords is stored in at least some of the first plurality of memory cells and a second plurality of codewords is stored in at least some of the second plurality of memory cells;
a mode register configured to store a per-row error correct and scrub (ECS) count enable signal; and
ECS logic configured to:
count a first number of the first plurality of codewords along the first word line which contain an error when the per-row ECS count enable signal is active; and
count a second number of the second plurality of codewords along the second word line which contain an error when the per-row ECS count enable signal is active,
wherein:
a first portion of the first plurality of memory cells is used to store data;
a second portion of the first plurality of memory cells is used to store metadata associated with the data;
a third portion of the first plurality of memory cells is used neither for data or metadata, and
the ECS logic is configured to store the first number in the third portion.
15 . The apparatus of claim 14 , wherein:
a fourth portion of the second plurality of memory cells is used to store data;
a fifth portion of the second plurality of memory cells is used to store metadata associated with the data;
a sixth portion of the second plurality of memory cells is used neither for data or metadata; and
the ECS logic is configured to store the second number in the sixth portion.
16 . The apparatus of claim 14 , wherein:
the mode register is configured to store a per-row ECS address that specifies selected ones of the first plurality of memory cells used to store the first number; and
the per-row ECS address specifies a column address signal associated with selected ones of the plurality of bit lines.
17 . The apparatus of claim 16 , further comprising a fuse array configured to store the per-row ECS address that is loaded into the mode register.
18 . The apparatus of claim 14 , wherein the ECS logic is configured to collect other ECS information regardless of whether the per-row ECS count enable signal is active or not, the other ECS information comprising at least one of an error count (EC) count or an errors per count (EpRC) count.
19 . An apparatus, comprising:
a memory array comprising a first plurality of memory cells at the intersection of a first word line and a plurality of bit lines and a second plurality of memory cells at the intersection of a second word line and the plurality of bit lines, wherein a first plurality of codewords is stored in at least some of the first plurality of memory cells and a second plurality of codewords is stored in at least some of the second plurality of memory cells;
a mode register configured to store a per-row error correct and scrub (ECS) count enable signal; and
ECS logic configured to:
count a first number of the first plurality of codewords along the first word line which contain an error when the per-row ECS count enable signal is active;
count a second number of the second plurality of codewords along the second word line which contain an error when the per-row ECS count enable signal is active; and
store the first number and the second number in one or more stranded columns of the memory array, wherein the one or more stranded columns are configured as non-addressable memory in at least one mode of the apparatus.
20 . The apparatus of claim 19 , wherein:
a first portion of the first plurality of memory cells is used to store data;
a second portion of the first plurality of memory cells is used to store metadata associated with the data;
a third portion of the first plurality of memory cells is used neither for data or metadata; and
the ECS logic is configured to store the first number in the third portion.
21 . The apparatus of claim 19 , wherein the ECS logic is configured to collect other ECS information regardless of whether the per-row ECS count enable signal is active or not, the other ECS information comprising at least one of an error count (EC) count or an errors per row count (EpRC) count.