Planar transistor device comprising at least one layer of a two-dimensional (2D) material
A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.
1. A planar transistor device comprising a gate having a gate length that extends in a gate length direction and a gate width that extends in a gate width direction, the transistor comprising:
a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface;
a gate cap on the gate structure;
a channel region;
a source region;
a drain region; and
a plurality of layers of a two-dimensional (2D) material in a vertically stacked layer and positioned in at least one of the source region and the drain region, wherein the at least one layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the at least one layer of 2D material in the gate length direction and across an entire width of the at least one layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the at least one layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate wherein an uppermost layer of the plurality of layers of 2D material in the source region and an uppermost layer of the plurality of layers of 2D material in the drain region are substantially co-planar with an upper surface of the gate cap; and
wherein the gate structure is positioned on a substantially planar upper surface of the semiconductor substrate and wherein the at least one layer of 2D material is positioned across an entirety of the source region and across an entirety of the drain region, wherein a portion of the semiconductor substrate positioned below the gate structure comprises the channel region and wherein the channel region is substantially free of the of the at least one layer of 2D material.
2. The planar transistor device of claim 1 , wherein the device further comprises a first conductive source/drain contact structure that is conductively coupled to an uppermost layer of the plurality of layers of 2D material in the source region and a second conductive source/drain contact structure that is conductively coupled to an uppermost layer of the plurality of layers of 2D material in the drain region.
3. The planar transistor device of claim 2 , wherein at least one sidewall spacer is positioned between the gate structure and the at least one layer of 2D material in the source region and the at least one layer of 2D material in the drain region.
4. The planar transistor device of claim 2 , wherein an uppermost layer of the plurality of layers of 2D material in the source region and an uppermost layer of the plurality of layers of 2D material in the drain region has an upper surface that is positioned at a level that is above a level of an upper surface of the gate structure.
5. The planar transistor device of claim 2 , further comprising a first isolation structure with a first portion adjacent the plurality of layers of 2D material in the source region and a second portion adjacent a first side of the channel region; and
a second isolation structure with a first portion adjacent the plurality of layers of 2D material in the drain region and a second portion adjacent a second side of the channel region.
6. The planar transistor device of claim 2 , wherein each of the plurality of layers of 2D material have a substantially same vertical thickness.
7. A planar transistor device comprising a gate having a gate length that extends in a gate length direction and a gate width that extends in a gate width direction, the transistor comprising:
a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface;
a gate cap on the gate structure;
a channel region;
a source region;
a drain region; and
a plurality of layers of a two-dimensional (2D) material that is in a vertically stacked layer and positioned in at least one of the source region and the drain region, wherein the at least one layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the at least one layer of 2D material in the gate length direction and across an entire width of the at least one layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the at least one layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate wherein an uppermost layer of the plurality of layers of 2D material in the source region and an uppermost layer of the plurality of layers of 2D material in the drain region are substantially co-planar with an upper surface of the gate cap,
wherein the plurality of layers of 2D material extends across an entirety of the source region, an entirety of the channel region and an entirety of the drain region, and
wherein the device further comprises a first conductive source/drain contact structure that is conductively coupled to an uppermost layer of the plurality of layers of 2D material in the source region and a second conductive source/drain contact structure that is conductively coupled to an uppermost layer of the plurality of layers of 2D material in the drain region.
8. The planar transistor device of claim 7 , wherein at least one sidewall spacer is positioned between the gate structure and the plurality of layers of 2D material in the source region and the plurality of layers of 2D material in the drain region.
9. The planar transistor device of claim 7 , further comprising a first isolation structure with a first portion adjacent the plurality of layers of 2D material in the source region and a second portion adjacent a first side of the channel region; and
a second isolation structure with a first portion adjacent the plurality of layers of 2D material in the drain region and a second portion adjacent a second side of the channel region.
10. The planar transistor device of claim 9 , wherein a bottommost surface of the first isolation structure and a bottommost surface of the second isolation structure are each beneath a bottommost surface of the plurality of layers of 2D material.
11. The planar transistor device of claim 7 , further comprising a pair of isolation structures on opposing horizontal sides of the channel region and beneath the plurality of layers of 2D material.
12. The planar transistor device of claim 7 , wherein each of the plurality of layers of 2D material have a substantially same vertical thickness.
13. A planar transistor device comprising a gate having a gate length that extends in a gate length direction and a gate width that extends in a gate width direction, the transistor comprising:
a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, the gate structure comprising an upper surface;
a gate cap on the gate structure;
a channel region;
a source region;
a drain region;
a plurality of layers of two-dimensional (2D) material in a vertically stacked layer, that is positioned across an entirety of the source region and across an entirety of the drain region, wherein the channel region is substantially free of the plurality of layers of 2D material, wherein each of the plurality of layers of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the plurality of layers of 2D material in the gate length direction and across an entire width of the plurality of layers of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of each of the plurality of layers of 2D material are positioned approximately parallel to the substantially planar upper surface of the semiconductor substrate, wherein an uppermost layer of the plurality of layers of 2D material in the source region and an uppermost layer of the plurality of layers of 2D material in the drain region are substantially co-planar with an upper surface of the gate cap; and
a sidewall spacer positioned adjacent the gate structure between the plurality of layers of 2D material in the source region and the plurality of layers of 2D material in the drain region.
14. The planar transistor device of claim 13 , wherein the plurality of layers of 2D material positioned is in a vertically stacked arrangement and wherein the device further comprises a first conductive source/drain contact structure that is conductively coupled to an uppermost layer of the plurality of layers of 2D material in the source region and a second conductive source/drain contact structure that is conductively coupled to an uppermost layer of the plurality of layers of 2D material in the drain region.
15. The planar transistor device of claim 13 , wherein an uppermost layer of the plurality of layers of 2D material in the source region and an uppermost layer of the plurality of layers of 2D material in the drain region has an upper surface that is positioned at a level that is above a level of an upper surface of the gate structure.
16. The planar transistor device of claim 13 , wherein the semiconductor substrate includes a semiconductor-on-insulator substrate.
17. The planar transistor device of claim 13 , further comprising a first isolation structure with a first portion adjacent the plurality of layers of 2D material in the source region and a second portion adjacent a first side of the channel region; and
a second isolation structure with a first portion adjacent the plurality of layers of 2D material in the drain region and a second portion adjacent a second side of the channel region.
18. The planar transistor device of claim 17 , wherein a bottommost surface of the first isolation structure and a bottommost surface of the second isolation structure are each beneath a bottommost surface of the plurality of layers of 2D material.
19. The planar transistor device of claim 13 , wherein each of the plurality of layers of 2D material have a vertical thickness that is substantially the same.