Granted Patent B2

US 12,744,104 · App. 18/430,406 · Granted Sep 22, 2026

Inventor: Sujeet Ayyapureddi (Boise, ID)

Assignee: Micron Technology, Inc.

G11C29/76G11C29/789

Abstract

Claims (41)

1 . An apparatus comprising:

an address decoder configured to receive a column address comprising a plurality of bits; and

a memory array comprising a plurality of column planes, wherein a portion of individual ones of the plurality of column planes are configured to store metadata and additional error correction (ECC) data,

wherein the metadata is associated with data associated with other portions of the plurality of column planes,

wherein the metadata is mapped to the data by a metadata address based on a portion of the column address, wherein the portion comprises less than all of the plurality of bits.

2 . The apparatus of claim 1 , wherein the metadata is stored in half of the plurality of column planes.

3 . The apparatus of claim 1 , wherein a seventh, an eighth, and a ninth bit of the column address indicate a column plane of the plurality of column planes including the metadata mapped to the data of another portion of the plurality of column planes, and a fourth, fifth, and sixth bit of the column address indicate a location of the metadata in the column plane mapped to the data of another portion of the plurality of column planes, wherein the metadata associated with the data of a first eight consecutive column selects of a plurality of column selects is stored in a first column plane of the plurality of column planes and the metadata associated with a second eight consecutive column selects of the plurality of column selects is stored in a second column plane of the plurality of column planes, the metadata associated with the data of a third eight consecutive column selects of the plurality of column selects is stored in a third column plane of the plurality of column planes.

4 . The apparatus of claim 1 , wherein a seventh, an eighth, a ninth, and a tenth bit of the column address indicates a column plane of the plurality of column planes including the metadata mapped to the data of another portion of the plurality of column planes, and a fourth, fifth, and sixth bit indicate a location of the metadata in the column plane mapped to the data of another portion of the plurality of column planes.

5 . The apparatus of claim 4 , wherein the metadata is stored in locations of the portion of the individual ones of the plurality of column planes associated with an address where the tenth bit is a first value.

6 . The apparatus of claim 4 , wherein an address of the column plane associated with the metadata comprises the ninth bit as a most significant bit, the eighth bit as a second most significant bit, the tenth bit as a third most significant bit, and the seventh bit as a least significant bit.

7 . The apparatus of claim 4 , wherein:

the metadata associated with the data of a first eight consecutive column selects of a plurality of column selects is stored in a first column plane of the plurality of column planes,

the metadata associated with a second eight consecutive column selects of the plurality of column selects is stored in a second column plane of the plurality of column planes,

the metadata associated with the data of a third eight consecutive column selects of the plurality of column selects is stored in a fifth column plane of the plurality of column planes,

the metadata associated with the data of a fourth eight consecutive column selects of the plurality of column selects is stored in a sixth column plane of the plurality of column planes,

the metadata associated with the data of a fifth eight consecutive column selects of the plurality of column selects is stored in a ninth column plane of the plurality of column planes,

the metadata associated with the data of a sixth eight consecutive column selects of the plurality of column selects is stored in a tenth column plane of the plurality of column planes,

the metadata associated with the data of a seventh eight consecutive column selects of the plurality of column selects is stored in a thirteenth column plane of the plurality of column planes, and

the metadata associated with the data of a final seven consecutive column selects of the plurality of column selects is stored in a fourteenth column plane of the plurality of column planes.

8 . The apparatus of claim 1 , wherein the portion of the plurality of column planes storing the metadata is associated with a first column select of a plurality of column selects and the data is associated with other ones of the plurality of column selects.

9 . The apparatus of claim 1 , further comprising a mode register configured to receive the column address and generate the metadata address.

10 . A method comprising:

receiving a column address at a memory device;

generating a metadata address based on a portion of the column address, wherein the portion is less than an entirety of the column address;

retrieving from a memory array of the memory device, metadata associated with the metadata address and additional ECC data associated with a same column select as the metadata;

retrieving from the memory array, data associated with the column address; and

providing, from the memory device, the data and the metadata.

11 . The method of claim 10 , wherein the data is retrieved after the metadata.

12 . The method of claim 10 , wherein the metadata address is generated by a mode register of the memory device.

13 . The method of claim 10 , wherein generating the metadata address comprises selecting fourth through ninth bits of the column address as the metadata address.

14 . The method of claim 10 , wherein generating the metadata address comprises selecting a fourth through tenth bits of the column address as the metadata address.

15 . A system comprising:

a plurality of memory devices, wherein each memory device comprises:

a memory array comprising a plurality of column planes, wherein a portion of individual ones of the plurality of column planes are configured to store metadata and additional error correction (ECC) data,

wherein the metadata is associated with data associated with other portions of the plurality of column planes,

wherein the metadata is mapped to the data by a metadata address based on a portion of a column address comprising a plurality of bits, wherein the portion comprises less than all of the plurality of bits.

16 . The system of claim 15 , wherein each of the plurality of memory devices is configured to provide one bit of metadata.

17 . The system of claim 15 , wherein half of the plurality of memory devices are configured to provide one bit of metadata based, at least in part, on the column address.

18 . The system of claim 15 , further comprising a controller coupled to the plurality of memory devices, wherein the controller is configured to ignore the data, the metadata, or a combination thereof, from one or more of the plurality of memory devices based, at least in part, on the column address.

19 . The system of claim 15 , wherein the portion of the column address associated with the metadata address comprises six or seven bits.

20 . The system of claim 15 , wherein a seventh, an eighth, and a ninth bit of the column address indicate a column plane of the plurality of column planes including the metadata mapped to the data of another portion of the plurality of column planes, and a fourth, fifth, and sixth bit of the column address indicate a location of the metadata in the column plane mapped to the data of another portion of the plurality of column planes.

Assignments (1)

Continuity (2)

References Cited (264)