Granted Patent B2

US 12,699,240 · App. 19/284,688 · Granted Aug 4, 2026

Inventors: Philip Winterbottom (San Jose, CA); David Lazovsky (Los Gatos, CA); Ankur Aggarwal (Pleasanton, CA); Martinus Bos (San Jose, CA); Subal Sahni (La Jolla, CA)

Assignee: Sicily Merger Sub II, Inc.

G02B6/4295G01K7/023G01K7/028G01K7/14G02B6/4246G02B6/428G02B6/43G02F1/0113G02F1/0123G02F1/0157G02B6/4245

Abstract

Claims (29)

1 . A package, comprising:

a package substrate;

a bridging element disposed in the package substrate, the bridging element providing an optical bridge among a plurality of dies;

an analog/mixed signal (AMS) block coupled to the bridging element, the AMS block configured for implementing a data serialization interface or a data deserialization interface between the dies and the bridging element;

a photonic network, disposed in the bridging element, comprising a plurality of photonic paths;

a first photonic transceiver disposed in the bridging element, the first photonic transceiver optically coupled to the photonic network and electrically coupled to the AMS block;

a second photonic transceiver disposed in the bridging element, the second photonic transceiver optically coupled to the photonic network and electrically coupled to the AMS block;

an optical input disposed in the bridging element, the optical input providing an optical connection to light from an external device; and

a splitter disposed in the bridging element, the splitter coupled to the optical input via the photonic network and further coupled to the first and the second photonic transceivers via the photonic network, and wherein the splitter is configured for distributing the light over different photonic paths in the photonic network, wherein

a distance between the AMS block and the bridging element is smaller than 50 μm.

2 . The package of claim 1 , further including a plurality of AMS blocks comprising a first serializer, a first deserializer, a second serializer, and a second deserializer, and wherein the first serializer and first deserializer are coupled to a first die through a first digital interface, and the second serializer and second deserializer are coupled to a second die through a second digital interface.

3 . The package of claim 2 , wherein the first or second digital interface comprises one of UCIe (Universal Chiplet Interconnect Express) or PCIe (Peripheral Component Interconnect Express).

4 . The package of claim 1 , wherein the optical input is coupled to the external device with one or more optical fibers.

5 . The package of claim 4 , wherein the optical input comprises one of an edge coupler, a grating coupler, a graded index lens coupler, a fiber Bragg grating coupler, a micro-lens array coupler, an evanescent wave coupler, an adiabatic coupler, a wavelength division multiplexing coupler, a prism coupler, a butt coupler, an end-fire coupler, or a V-groove coupler.

6 . The package of claim 5 , wherein the one or more optical fibers comprise a fiber array unit that is optically coupled to an edge coupler.

7 . The package of claim 1 , wherein the photonic network is implemented using one or more waveguides.

8 . The package of claim 1 , wherein the external device comprises one of a light engine or an electrical device.

9 . The package of claim 1 , wherein one or more of the electrical interconnects comprise a redistribution layer.

10 . The package of claim 9 , wherein the redistribution layer comprises one or more of electrical interconnections or through-glass vias between the dies and the bridging element.

11 . The package of claim 1 , wherein the package substrate comprises a printed circuit board, an interposer, or a motherboard.

12 . The package of claim 1 , wherein the first photonic transceiver or the second photonic transceiver comprises a modulator and a photodetector.

13 . The package of claim 12 , wherein the modulator comprises one of a Mach-Zehnder interferometer, electro-absorption modulator, or a ring modulator.

14 . The package of claim 12 , wherein the modulator is configured to modulate using one of a non-return-to-zero or a pulse amplitude modulation scheme.

15 . The package of claim 12 , wherein the AMS block is aligned with the dies such that the data serialization interface or deserialization interface is accessible by a compute element or memory region disposed in a central region of a die.

16 . The package of claim 12 , wherein the AMS block further comprises a modulator driver.

17 . The package of claim 1 , wherein the AMS block further comprises a transmit bonding engine and a receive bonding engine.

18 . The package of claim 1 , wherein the AMS block further comprises a transimpedance amplifier.

19 . The package of claim 1 , wherein the AMS block further comprises a slicer.

20 . The package of claim 1 , wherein the AMS block further comprises a gain control.

Assignments (2)

Continuity (10)

References Cited (400)