Granted Patent B2

US 12,199,082 · App. 18/498,718 · Granted Jan 14, 2025

Inventors: Min Tao (San Jose, CA); Liang Wang (Milpitas, CA); Rajesh Katkar (Milpitas, CA); Cyprian Emeka Uzoh (San Jose, CA)

Assignee: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC

H01L25/167H01L21/02118H01L21/3212H01L24/08H01L24/80H01L25/105H01L25/18H01L27/1214H01L27/156H01L33/007H01L33/0093H01L33/06H01L33/32H01L33/44H01L33/46H01L33/62H01L2224/08145H01L2224/80013H01L2224/80355H01L2224/80357H01L2933/0016H01L2933/0025H01L2933/0066

Abstract

Claims (27)

1. A method of forming an optoelectronic assembly, comprising:

directly bonding a lower surface of a first substrate to an upper surface of a second substrate at a bonding interface, the first substrate comprising a plurality of optoelectronic devices;

after directly bonding, thinning the second substrate from a lower side opposite the upper surface of the second substrate;

after directly bonding, etching non-device portions of the second substrate from the lower side between device portions of the second substrate; and

refilling spaces between the device portions with a dielectric material.

2. The method of claim 1 , wherein directly bonding comprises

directly bonding a first dielectric surface of the first substrate to a second dielectric surface of the second substrate at the bonding interface; and

directly bonding first electrical contacts of the first substrate to second electrical contacts of the second substrate at the bonding interface.

3. The method of claim 2 , wherein directly bonding the first dielectric surface with the second dielectric surface comprises oxide bonding.

4. The method of claim 1 , wherein directly bonding comprises hybrid bonding.

5. The method of claim 1 , further comprising forming electrical connections through the dielectric material to the optoelectronic devices of the first substrate.

6. The method of claim 1 , wherein directly bonding comprises annealing the first and second substrate.

7. The method of claim 6 , wherein annealing is conducted between about 100° C. and 200° C.

8. The method of claim 1 , further comprising plasma activating at least one of the lower surface of the first substrate and the upper surface of the second substrate prior to directly bonding.

9. The method of claim 8 , further comprising planarizing each of the lower surface of the first substrate and the upper surface of the second substrate prior to directly bonding.

10. The method of claim 1 , wherein the first substrate comprises a compound semiconductor substrate and the second substrate comprises a silicon substrate.

11. The method of claim 10 , wherein the optoelectronic devices comprise an array of light emitting diodes, and the device portions comprise transistors forming part of light emitting diode driver circuitry.

12. The method of claim 10 , wherein the first substrate comprises a ternary III-V semiconductor substrate.

13. The method of claim 1 , further comprising integrating a plurality of optical elements over an upper surface of the first substrate opposite the lower surface of the first substrate.

14. The method of claim 13 , wherein optical elements comprise at least one of a beam steering element or a beam shaping element.

15. The method of claim 13 , further comprising directly bonding a transparent substrate to the upper surface of the first substrate and positioning the transparent substrate between the optoelectronic devices and the optical elements.

16. The method of claim 13 , further comprising integrating one or more second optical elements with the first substrate.

17. The method of claim 16 , wherein the one or more second optical elements comprise a waveguide integrated at a side edge of the first substrate.

18. The method of claim 1 , wherein etching the non-device portions comprises exposing a portion of the first substrate.

19. The method of claim 1 , further comprising processing the lower side of the second substrate after the etching.

20. The method of claim 19 , wherein the processing comprises providing electrical connections for the device portions.

21. The method of claim 19 , wherein the processing comprises providing one or more build-up layers on the lower side of the second substrate.

Assignments (3)

Continuity (6)

References Cited (400)