Direct-bonded LED structure contacts and substrate contacts
Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.
1. A process, comprising:
fabricating an array of LED structures, wherein each LED structure includes coplanar electrical contacts for p-type and n-type semiconductors on a first bonding surface; and
direct-bonding at least the coplanar electrical contacts of the first bonding surfaces of the array of LED structures to electrical contacts located on a substrate, wherein the electrical contacts on the substrate are in communication with a driver circuit within the substrate to individually control each LED structure in the array of LED structures.
2. The process of claim 1 , further comprising direct-bonding at least the coplanar electrical contacts of the first bonding surfaces of the array of LED structures to electrical contacts of an array of driver circuits.
3. The process of claim 2 , wherein each LED structure in the array of LED structures and each connection to an instance of a driver circuit in the array of driver circuits are in a 1:1 ratio.
4. The process of claim 2 , wherein each LED structure has an illumination area approximately a size of a pixel of a video display.
5. The process of claim 4 , wherein the video display comprises a high-resolution video display.
6. The process of claim 2 , wherein each LED structure has an illumination area approximately a size of a smallest controllable element of an image represented on a display.
7. The process of claim 2 , wherein the LED structures in the array of LED structures comprise micro-LEDs, each micro-LED having an illumination area approximately a size of a pixel of a high-resolution video display, or an illumination area approximately a size of a smallest controllable element of an image represented on the high-resolution video display.
8. The process of claim 1 , further comprising direct-bonding a first chip comprising the LED structures with coplanar electrical contacts with a second chip comprising the electrical contacts in communication with a driver circuit for the array of the LED structures.
9. A process, comprising:
building semiconductor layers of LED structures on a first substrate;
patterning the first substrate with a resist and etching the first substrate to expose an n-type semiconductive layer of each LED structure;
depositing a silicon oxide layer to cover both a p-type semiconductive layer and the exposed n-type semiconductive layer of each LED structure;
patterning and etching the silicon oxide over the p-type semiconductive layer and the n-type semiconductive layer of each LED structure to form cavities in the silicon oxide down to the surfaces of the p-type semiconductive layer and the n-type semiconductive layer of each LED structure;
metalizing the cavities in the silicon oxide;
planarizing the silicon oxide and the metalized cavities to make a flat bonding surface with coplanar contacts of the p-type semiconductive layer and the n-type semiconductive layer of each LED structure;
plasma-activating a surface of the first substrate;
bonding the activated surface to a second substrate; and
annealing the bonded substrate to make a direct-bonded LED array display.
10. The process of claim 9 , wherein each LED structure of the first substrate is direct-bonded to a conductive contact of the second substrate, wherein metal regions and dielectric regions of each LED structure on the first substrate are direct-bonded to respective metal regions and dielectric regions of the second substrate.
11. The process of claim 9 , further comprising thinning a thin-film transistor (TFT) backplane of the direct-bonded LED array display.
12. The process of claim 11 , further comprising coating the thinned backplane with a polyimide (PI) layer for protection.
13. The process of claim 12 , further comprising removing the first substrate through a laser-lift-off process and coating the remaining surface with a flexible organic substrate, to make a transparent and flexible direct-bonded LED array display.
14. A process, comprising:
forming semiconductor layers of LED structures on a surface of a first substrate;
forming an exposed n-type semiconductive layer of each LED structure within the semiconductor layers of each LED structure;
forming an exposed p-type semiconductive layer of each LED structure within the semiconductor layers of each LED structure;
forming a planarized damascene layer with coplanar damascene conductive areas respectively contacting the exposed n-type semiconductive layer and the exposed p-type semiconductive layer of each LED structure; and
bonding the coplanar damascene conductive areas to a surface of a second substrate.
15. The process of claim 14 , further comprising:
plasma-activating the planarized damascene layer before the bonding to the surface of the second substrate, wherein the bonding comprises a direct-bonding process; and
after the direct-bonding process, annealing the direct-bonded damascene layer to finish the direct-bonding process.
16. The process of claim 14 , wherein the coplanar damascene conductive areas for contacting the exposed n-type semiconductive layer and the exposed p-type semiconductive layer of a single LED structure are within a horizontal planar footprint of the single LED structure.
17. The process of claim 14 , wherein forming the semiconductor layers of LED structures on the surface of the first substrate comprises forming an array of micro-LEDs.
18. The process of claim 17 , wherein forming the micro-LEDs comprises forming micro-LED structures having an illumination area approximately a size of a pixel of a high-resolution video display, or an illumination area approximately a size of a smallest controllable element of an image represented on the high-resolution video display.
19. The process of claim 17 , wherein forming the micro-LED structures comprises forming a contiguous semiconductor doped layer to provide active regions for multiple micro-LED structures in the array.
20. The process of claim 17 , further comprising:
bonding the coplanar damascene conductive areas to an array of driver circuits, wherein each micro-LED is individually controlled by the array of driver circuits.
21. The process of claim 20 , wherein the array of micro-LEDs and the array of driver circuits are direct hybrid bonded together through oxide-to-oxide direct bonds between respective dielectric areas and through metal-to-metal direct bonds between the coplanar damascene conductive areas and conductive areas of the second surface.
22. The process of claim 14 , further comprising:
thinning a thin-film transistor (TFT) backplane of the bonded surfaces; and
coating the thinned backplane with a polyimide (PI) layer for protection.
23. The process of claim 22 , further comprising:
removing the substrate through a laser-lift-off process and coating a surface exposed by the laser-lift-off process with a flexible organic substrate, to make a transparent and flexible direct-bonded micro-LED array.