IP Library › Granted Patent US 12,262,565
Granted Patent B2
US 12,262,565 · App. 18/259,947 · Granted Mar 25, 2025

Light detecting device and electronic device

Inventors: Hirofumi Yamashita (Kanagawa, JP); Chihiro Tomita (Kanagawa, JP); Harumi Tanaka (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H10F39/811H10F39/8037H10F39/807
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Quick Facts
Patent No.
US 12,262,565
App. No.
18/259,947
Granted
Mar 25, 2025
Kind
B2
Abstract

A light detecting device includes a semiconductor layer having a first surface and a second surface located on opposite sides to each other in a thickness direction, and a photoelectric conversion cell provided in the semiconductor layer and partitioned by a first isolation region. The photoelectric conversion cell includes a first photoelectric conversion region adjacent to a second photoelectric conversion region in plan view and each having a photoelectric conversion unit and a transfer transistor, a second isolation region arranged between the first photoelectric conversion region and the second photoelectric conversion region in plan view and extending in a thickness direction of the semiconductor layer, and an element formation region partitioned on the first surface side of the semiconductor layer by a third isolation region and provided with a pixel transistor. The element formation region extends over the first and second photoelectric conversion regions in plan view.

Claims (18)

1. A light detecting device, comprising:

a first pixel provided on a semiconductor substrate; and

a trench including a first region that isolates the first pixel from an adjacent pixel and a second region in which a first photoelectric conversion unit provided in the first pixel is shielded from a second photoelectric conversion unit provided in the first pixel,

wherein the first region encloses the first pixel,

wherein the second region has a first portion that protrudes from a first portion of the first region to extend between a first floating diffusion region and a second floating diffusion region provided in the first pixel in plan view,

wherein the second region has a second portion that protrudes from a second portion of the first region to extend between a first transistor and a second transistor provided in the first pixel in the plan view,

wherein the first portion of the first region is on a first side of the first pixel,

wherein the second portion of the first region is on a second side of the first pixel,

wherein the first side of the first pixel is opposite the second side of the first pixel, and

wherein the first portion of the second region and the second portion of the second region protrude toward a contact region between the first portion of the first region and the second portion of the first region and between the first portion of the second region and the second portion of the second region in the plan view.

2. The light detecting device according to claim 1 , wherein the first portion of the second region, the contact region, and the second portion of the second region are arranged in this order along a first direction in the plan view.

3. The light detecting device according to claim 2 , wherein a first contact, a gate electrode, and a second contact of the first transistor are arranged in this order along the first direction.

4. The light detecting device according to claim 3 , wherein a third contact, a gate electrode, and a fourth contact of the second transistor are arranged in this order along the first direction.

5. The light detecting device according to claim 1 , wherein the trench penetrates the semiconductor substrate.

6. The light detecting device according to claim 1 , wherein the contact region is provided at a center of the first pixel.

7. The light detecting device according to claim 1 , wherein the contact region is a p-type impurity region.

8. The light detecting device according to claim 1 , wherein the contact region is provided on the semiconductor substrate.

9. The light detecting device according to claim 1 , wherein the first and second regions do not overlap one another in the plan view.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2023
From: YAMASHITA, HIROFUMI; TOMITA, CHIHIRO; TANAKA, HARUMI
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 064116/0780 →
Priority Claims (1)
JP 2021-062418 · Mar 31, 2021 · national
Continuity (1)
Related Publication 20240038815A1 · Feb 1, 2024
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