IP Library › Granted Patent US 12,353,107
Granted Patent B2
US 12,353,107 · App. 18/510,963 · Granted Jul 8, 2025

Liquid crystal display device

Inventor: Hajime Kimura (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G02F1/136286G02F1/133528G09G3/20G09G3/3233G09G3/3677G11C19/28H10K10/482G02F1/133638G09G2300/0408G09G2300/0417G09G2300/0847G09G2310/0254G09G2310/0267G09G2310/0286G09G2310/0291G09G2310/08G09G2320/043H10K10/20
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Quick Facts
Patent No.
US 12,353,107
App. No.
18/510,963
Granted
Jul 8, 2025
Kind
B2
Abstract

To suppress a malfunction of a circuit due to deterioration in a transistor. In a transistor which continuously outputs signals having certain levels (e.g., L-level signals) in a pixel or a circuit, the direction of current flowing through the transistor is changed (inverted). That is, by changing the level of voltage applied to a first terminal and a second terminal (terminals serving as a source and a drain) every given period, the source and the drain are switched every given period. Specifically, in a portion which successively outputs signals having certain levels (e.g., L-level signals) in a circuit including a transistor, L-level signals having a plurality of different potentials (L-level signals whose potentials are changed every given period) are used as the signals having certain levels.

Claims (63)

1. A semiconductor device comprising:

a first circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,

wherein one of a source and a drain of the second transistor is electrically connected to the first wiring,

wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring,

wherein one of a source and a drain of the third transistor is electrically connected to a fourth wiring,

wherein the other of the source and the drain of the third transistor is electrically connected to the second wiring,

wherein a gate of the third transistor is directly connected to a gate of the first transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to the fourth wiring,

wherein a gate of the fourth transistor is directly connected to a gate of the second transistor,

wherein one of a source and a drain of the fifth transistor is directly connected to a gate of the second transistor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to a fifth wiring,

wherein a gate of the fifth transistor is directly connected to a gate of the first transistor,

wherein one of a source and a drain of the sixth transistor is directly connected to a gate of the first transistor,

wherein the other of the source and the drain of the sixth transistor is electrically connected to the fifth wiring,

wherein a gate of the sixth transistor is directly connected to a gate of the second transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to a gate of the second transistor,

wherein the other of the source and the drain of the seventh transistor is electrically connected to a sixth wiring,

wherein one of a source and a drain of the eighth transistor is electrically connected to the gate of the second transistor,

wherein the other of the source and the drain of the eighth transistor is electrically connected to the fifth wiring, wherein one of a source and a drain of the ninth transistor is directly connected to a gate of the seventh transistor,

wherein the other of the source and the drain of the ninth transistor is electrically connected to the sixth wiring,

wherein a gate of the ninth transistor is electrically connected to the sixth wiring,

wherein one of a source and a drain of the tenth transistor is directly connected to a gate of the seventh transistor,

wherein the other of the source and the drain of the tenth transistor is electrically connected to the fifth wiring,

wherein a gate of the tenth transistor is electrically connected to the gate of the first transistor,

wherein one of a source and a drain of the eleventh transistor is electrically connected to the gate of the first transistor,

wherein one of a source and a drain of the twelfth transistor is electrically connected to the gate of the first transistor, and

wherein the other of the source and the drain of the twelfth transistor is electrically connected to the fifth wiring.

2. The semiconductor device according to claim 1 ,

wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor comprises a plurality of gate electrodes and a plurality of channel regions electrically connected in series.

3. The semiconductor device according to claim 1 ,

wherein each of a channel region of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor comprises polycrystalline silicon.

4. The semiconductor device according to claim 1 , further comprising a second circuit and a third circuit,

wherein a gate of the eighth transistor is electrically connected to the second circuit,

wherein a gate of the eleventh transistor is electrically connected to the second circuit, and

wherein a gate of the twelfth transistor is electrically connected to the third circuit.

5. The semiconductor device according to claim 1 , further comprising a second circuit and a third circuit,

wherein a gate of the eighth transistor is electrically connected to a seventh wiring,

wherein a gate of the eleventh transistor is electrically connected to the seventh wiring,

wherein a gate of the twelfth transistor is electrically connected to an eighth wiring, and

wherein the fourth wiring is electrically connected to the second circuit and the third circuit.

6. The semiconductor device according to claim 1 ,

wherein the second wiring is configured to supply a clock signal to the first circuit.

7. A semiconductor device comprising:

a first circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein one of a source and a drain of the second transistor is electrically connected to the first wiring,

wherein one of a source and a drain of the third transistor is electrically connected to a fourth wiring,

wherein a gate of the third transistor is directly connected to a gate of the first transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to the fourth wiring,

wherein a gate of the fourth transistor is directly connected to a gate of the second transistor,

wherein one of a source and a drain of the fifth transistor is directly connected to a gate of the second transistor,

wherein a gate of the fifth transistor is directly connected to a gate of the first transistor,

wherein one of a source and a drain of the sixth transistor is directly connected to a gate of the first transistor,

wherein a gate of the sixth transistor is directly connected to a gate of the second transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the eighth transistor is electrically connected to the gate of the second transistor,

wherein one of a source and a drain of the ninth transistor is directly connected to a gate of the seventh transistor,

wherein a gate of the ninth transistor is electrically connected to a sixth wiring, wherein one of a source and a drain of the tenth transistor is directly connected to a gate of the seventh transistor,

wherein a gate of the tenth transistor is electrically connected to the gate of the first transistor,

wherein one of a source and a drain of the eleventh transistor is electrically connected to the gate of the first transistor, and

wherein one of a source and a drain of the twelfth transistor is electrically connected to the gate of the first transistor.

Priority Claims (1)
JP 2008-292197 · Nov 14, 2008 · national
Continuity (7)
Continuation 17518001 · Nov 3, 2021
Continuation 17116731 · Dec 9, 2020
Continuation 16519110 · Jul 23, 2019
Continuation 15668737 · Aug 4, 2017
Continuation 13488475 · Jun 5, 2012
Division 12614926 · Nov 9, 2009
Related Publication 20240168349A1 · May 23, 2024
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