Granted Patent B2

US 12,501,776 · App. 18/701,696 · Granted Dec 16, 2025

Inventors: Takanori Matsuzaki (Kanagawa, JP); Tatsuya Onuki (Kanagawa, JP); Kiyoshi Kato (Kanagawa, JP); Yuki Okamoto (Kanagawa, JP); Shunpei Yamazaki (Tokyo, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

H10K59/1213G09G3/3233G09G2300/0465G09G2300/0842

Abstract

Claims (64)

1 . A display apparatus comprising:

a first layer;

a second layer over the first layer; and

a third layer over the second layer,

wherein the first layer comprises a functional circuit,

wherein the second layer comprises a display unit comprising a plurality of pixels,

wherein the third layer comprises a memory unit comprising a plurality of memory cells,

wherein each of the plurality of pixels comprises a pixel circuit and a light-emitting element over the pixel circuit,

wherein the functional circuit comprises a display unit driver circuit, and

wherein the memory unit is configured to store image data that is to be output through the display unit driver circuit to the display unit.

2 . The display apparatus according to claim 1 ,

wherein one of the plurality of memory cells comprises:

a first transistor configured to retain a potential corresponding to the image data; and

a second transistor configured to read the potential,

wherein the first transistor is provided in the third layer, and

wherein the second transistor is provided in the first layer.

3 . The display apparatus according to claim 2 ,

wherein a semiconductor layer comprising a channel formation region of the first transistor comprises a metal oxide, and

wherein a semiconductor layer comprising a channel formation region of the second transistor comprises silicon.

4 . The display apparatus according to claim 1 ,

wherein the display unit driver circuit is provided in a region overlapping with the display unit.

5 . The display apparatus according to claim 1 ,

wherein the functional circuit comprises a control circuit, a sensor circuit, a communication circuit, and an input/output circuit.

6 . A display apparatus comprising:

a first layer; and

a second layer over the first layer,

wherein the first layer comprises:

a display unit driver circuit;

a memory unit driver circuit;

a control circuit; and

at least one of a sensor circuit, a communication circuit, and an input/output circuit,

wherein the second layer comprises:

a display unit comprising a plurality of pixels; and

a memory unit comprising a plurality of memory cells,

wherein each of the plurality of pixels comprises a pixel circuit and a light-emitting element over the pixel circuit,

wherein the memory unit is configured to store image data that is to be output through the display unit driver circuit to the display unit, and

wherein the display unit driver circuit, the memory unit driver circuit, the control circuit, and the one of the sensor circuit, the communication circuit, and the input/output circuit overlaps with the display unit.

7 . The display apparatus according to claim 6 ,

wherein one of the plurality of memory cells comprises:

a first transistor configured to retain a potential corresponding to the image data; and

a second transistor configured to read the potential,

wherein the first transistor is provided in the second layer, and

wherein the second transistor is provided in the first layer.

8 . The display apparatus according to claim 7 ,

wherein a semiconductor layer comprising a channel formation region of the first transistor comprises a metal oxide, and

wherein a semiconductor layer comprising a channel formation region of the second transistor comprises silicon.

9 . The display apparatus according to claim 6 ,

wherein, in a top view of the display apparatus, a first memory cell of the plurality of memory cells and a second memory cell of the plurality of memory cells sandwich the display unit.

10 . The display apparatus according to claim 6 ,

wherein the display unit comprises a plurality of sub-display units, and

wherein the number of times of image rewriting of image data per unit time in a first sub-display unit of the plurality of sub-display units is smaller than the number of times of image rewriting of image data per unit time in a second sub-display unit of the plurality of sub-display units.

11 . The display apparatus according to claim 6 ,

wherein one of the plurality of memory cells comprises:

a first transistor; and

a second transistor,

wherein the first transistor is provided in the second layer, and

wherein the second transistor is provided in the first layer.

12 . The display apparatus according to claim 11 ,

wherein a semiconductor layer comprising a channel formation region of the first transistor comprises a metal oxide, and

wherein a semiconductor layer comprising a channel formation region of the second transistor comprises silicon.

13 . The display apparatus according to claim 8 ,

wherein the metal oxide comprises indium.

14 . The display apparatus according to claim 12 ,

wherein the metal oxide comprises indium.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (115)