Semiconductor structure and forming method thereof
A semiconductor structure is provided. The semiconductor structure includes a first die and a second die. The first die includes a substrate, an interconnection structure and a capacitor structure. The substrate has a front-side surface and a back-side surface. The interconnection structure is disposed over the front-side surface. The capacitor structure extends from the back-side surface to the front-side surface and into the interconnection structure. The second die is disposed over the back-side surface and is bonded to the first die. A method for forming a semiconductor structure is also provided.
1 . A method for forming a semiconductor structure, comprising:
receiving a first die having a first substrate and a first interconnection structure over the first substrate, wherein the first substrate has a first front-side surface and a first back-side surface;
bonding a second die to the first die, the second die having a second substrate and a second interconnection structure over the second substrate;
forming a trench penetrating through the first substrate and the first interconnection structure, wherein the trench exposes a portion of the second die; and
forming a capacitor structure in the trench,
wherein the forming of the capacitor structure further comprises:
forming a first conductive layer lining sidewalls and an innermost surface of the trench and over the first back-side surface of the first substrate;
forming a first dielectric layer over the first conductive layer;
forming a second conductive layer over the first dielectric layer;
forming a second dielectric layer over the second conductive layer; and
patterning the second dielectric layer, the second conductive layer, the first dielectric layer and the first conductive layer to form the capacitor structure.
2 . The method of claim 1 , wherein the trench exposes a metal feature in the second interconnection structure.
3 . The method of claim 1 , wherein the trench exposes a dielectric layer of a bonding structure between the first interconnection structure and the second interconnection structure.
4 . The method of claim 1 , further comprising forming a liner in the trench lining a sidewall of the first substrate prior to forming the capacitor structure in the trench.
5 . A method for forming a semiconductor structure, comprising:
bonding a first die and a second die, wherein the first die comprises a first substrate and a first interconnection structure over the first substrate, and the second die comprises a second substrate and a second interconnection structure over the second substrate;
forming a first trench penetrating through the first die and a portion of the second die, wherein a metal feature of the second interconnection structure is exposed through the first trench; and
forming a capacitor structure in the first trench, wherein the capacitor structure is coupled to the metal feature of the second interconnection structure,
wherein the forming of the capacitor structure further comprises:
forming a first conductive layer lining sidewalls and an innermost surface of the first trench and over a back side surface of the first substrate;
forming a first dielectric layer over the first conductive layer;
forming a second conductive layer over the first dielectric layer;
forming a second dielectric layer over the second conductive layer; and
patterning the second dielectric layer, the second conductive layer, the first dielectric layer and the first conductive layer to form the capacitor structure.
6 . The method of claim 5 , further comprising forming a liner over sidewalls of the first trench prior to the forming of the capacitor structure.
7 . The method of claim 5 , further comprising performing a thinning operation to reduce a thickness of the first substrate prior to the forming of the first trench.
8 . The method of claim 5 , wherein the first conductive layer is coupled to the metal feature of the second interconnection structure.
9 . The method of claim 5 , further comprising:
forming a second trench in the first substrate, wherein the second trench exposes a metal feature of the first interconnection structure; and
forming a through-substrate-via (TSV) in the second trench.
10 . The method of claim 9 , wherein the second trench is separated from the first trench.
11 . The method of claim 5 , further comprising bonding the first die to a third die, wherein the third die comprises a third substrate and a third interconnection structure.
12 . The method of claim 11 , wherein the capacitor structure is disposed between the first substrate and the third interconnection structure.
13 . A method for forming a semiconductor structure, comprising:
bonding a first die and a second die, wherein the first die comprises a first substrate and a first interconnection structure over the first substrate, and the second die comprises a second substrate and a second interconnection structure over the second substrate;
forming a first trench penetrating through the first die and a portion of the second die, wherein metal features of the second interconnection structure are separated from the first trench; and
forming a capacitor structure in the first trench,
wherein the forming of the capacitor further comprises:
forming a first conductive layer lining sidewalls and an innermost surface of the first trench and over a back side surface of the first substrate;
forming a first dielectric layer over the first conductive layer;
forming a second conductive layer over the first dielectric layer;
forming a second dielectric layer over the second conductive layer; and
patterning the second dielectric layer, the second conductive layer, the first dielectric layer and the first conductive layer to form the capacitor structure.
14 . The method of claim 13 , further comprising forming a liner over sidewalls of the first trench prior to the forming of the capacitor structure.
15 . The method of claim 13 , further comprising performing a thinning operation to reduce a thickness of the first substrate prior to the forming of the first trench.
16 . The method of claim 13 , further comprising:
forming a second trench in the first substrate; and
forming a through-substrate-via (TSV) in the second trench,
wherein the second trench exposes a metal feature of the first interconnection structure, and
the second trench is separated from the first trench.
17 . The method of claim 13 , further comprising bonding the first die to a third die, wherein the third die comprises a third substrate and a third interconnection structure.
18 . The method of claim 17 , wherein the capacitor structure is electrically connected to the third interconnection structure.
19 . The method of claim 18 , wherein the third die comprises a semiconductor device.
20 . The method of claim 18 , wherein the capacitor structure is electrically connected to the semiconductor device through the third interconnection structure.