Radiation phase-detection autofocus (PDAF) performance
Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first pixel region and a second pixel region within a substrate. A first recess region is disposed along a back-side of the substrate within the first pixel region. The back-side of the substrate within the first pixel region is asymmetric about a center of the first pixel region in a cross-sectional view. A second recess region is disposed along the back-side of the substrate and within the second pixel region. The back-side of the substrate within the second pixel region is asymmetric about a center of the second pixel region in the cross-sectional view. The first recess region and the second recess region are substantially symmetric about a vertical line laterally between the first pixel region and the second pixel region.
1 . An integrated chip, comprising:
a first pixel region within a substrate;
a second pixel region within the substrate;
a third pixel region within the substrate;
a first recess region disposed along a back-side of the substrate within the first pixel region, the back-side of the substrate within the first pixel region being asymmetric about a center of the first pixel region in a cross-sectional view;
a second recess region disposed along the back-side of the substrate and within the second pixel region, the back-side of the substrate within the second pixel region being asymmetric about a center of the second pixel region in the cross-sectional view, wherein the first recess region and the second recess region are substantially symmetric about a vertical line laterally between the first pixel region and the second pixel region; and
a third recess region disposed along the back-side of the substrate and within the third pixel region, the back-side of the substrate within the third pixel region being substantially symmetric about a center of the third pixel region.
2 . The integrated chip of claim 1 , further comprising:
an isolation structure extending from the back-side of the substrate to within the substrate along opposing outer edges of the first pixel region and the second pixel region.
3 . The integrated chip of claim 2 , wherein the substrate has a first flat surface continuously extending between a first outer edge of the first recess region and the isolation structure and a second flat surface continuously extending between a second outer edge of the first recess region and the isolation structure, as viewed in the cross-sectional view.
4 . The integrated chip of claim 1 , wherein the first recess region is formed between a first pair of sidewalls of the substrate and the second recess region is formed between a second pair of sidewalls of the substrate, as viewed in the cross-sectional view.
5 . The integrated chip of claim 1 , wherein the first recess region is laterally between a first flat surface and a second flat surface of the substrate, the first flat surface continuously extending from an outer edge of the first pixel region to past a lateral center of the first pixel region.
6 . The integrated chip of claim 1 , wherein flat surfaces continuously extend between the third recessed region and opposing sides of the third pixel region.
7 . The integrated chip of claim 1 , further comprising:
a first micro-lens disposed along the back-side of the substrate over the first pixel region, wherein the first micro-lens is laterally off-centered from the first recess region; and
a second micro-lens disposed along the back-side of the substrate over the second pixel region, wherein the second micro-lens is laterally off-centered from the second recess region.
8 . The integrated chip of claim 7 , further comprising:
a first dielectric arranged along the back-side of the substrate and within the first recess region and the second recess region;
a grid structure arranged on the first dielectric; and
a second dielectric arranged on the first dielectric and having a bottom surface around the grid structure, wherein the bottom surface of the second dielectric completely covers the back-side of the substrate within both the first pixel region and the second pixel region, as viewed in the cross-sectional view.
9 . An integrated chip, comprising:
a substrate having a phase detection autofocus (PDAF) region and an image sensing region;
wherein the PDAF region comprises:
a first pixel region comprising a first diffuser disposed along a back-side of the substrate, the first diffuser being laterally between a first surface and a second surface of the substrate as viewed in a cross-section, and the first surface being longer than the second surface; and
a second pixel region comprising a second diffuser disposed along the back-side of the substrate and laterally between a third surface and a fourth surface as viewed in the cross-section, the third surface being longer than the fourth surface; and
wherein the image sensing region comprises an image sensing pixel region including a third diffuser disposed along the back-side of the substrate and laterally between a fifth surface and a sixth surface as viewed in the cross-section, the fifth surface being substantially equal in length to the sixth surface.
10 . The integrated chip of claim 9 , wherein the first diffuser, the second diffuser, and the third diffuser are triangular-shaped recesses as viewed in the cross-section.
11 . The integrated chip of claim 9 , wherein the first diffuser, the second diffuser, and the third diffuser are rectangular shaped recesses as viewed in the cross-section and in a plan-view.
12 . An integrated chip, comprising:
a substrate comprising a first pixel region and a second pixel region;
a first recess formed along a back-side of the substrate between a first set of sidewalls of the substrate within the first pixel region, the first recess being closer to a first outer edge of the first pixel region than to an opposing second outer edge of the first pixel region;
a second recess formed along the back-side of the substrate between a second set of sidewalls of the substrate within the second pixel region, the second recess being closer to a third outer edge of the second pixel region than to an opposing fourth outer edge of the second pixel region;
a first dielectric arranged along the back-side of the substrate and within the first recess and the second recess;
a grid structure arranged on the first dielectric, wherein the grid structure is laterally between the first pixel region and the second pixel region in a cross-sectional view; and
wherein the substrate comprises a first substantially flat surface that continuously extends from the first recess past a center of the first pixel region to the second outer edge of the first pixel region that faces the second pixel region and the substrate further comprises a second substantially flat surface that continuously extends from the second recess past a center of the second pixel region to the fourth outer edge of the second pixel region that faces the first pixel region.
13 . The integrated chip of claim 12 ,
wherein the first outer edge and the second outer edge of the first pixel region are separated along a first direction; and
wherein the first recess is arranged at substantially equal distances from opposing outer edges of the first pixel region along a second direction that is perpendicular to the first direction as viewed in a top-view.
14 . The integrated chip of claim 12 , further comprising:
an isolation structure vertically extending through the substrate and laterally separating the first pixel region from the second pixel region, wherein the first pixel region and the second pixel region are substantially symmetric about a line extending through the isolation structure.
15 . The integrated chip of claim 12 , further comprising:
a first micro-lens disposed along the back-side of the substrate over the first pixel region and laterally off-centered from the first recess, wherein the second pixel region is laterally outside of the first micro-lens.
16 . The integrated chip of claim 12 , wherein the first recess is off-centered from the center of the first pixel region along a first direction and wherein the first recess is substantially centered upon the center of the first pixel region along a second direction, the first direction and the second direction being perpendicular in a plan-view.
17 . The integrated chip of claim 12 , wherein the first recess is off-centered from the center of the first pixel region along a first direction and along a second direction, the first direction and the second direction being perpendicular in a plan-view.
18 . The integrated chip of claim 12 , further comprising:
a third recess formed between a third set of sidewalls of the substrate within an image sensing pixel region, the third recess being substantially equal distances from a fifth outer edge of the image sensing pixel region and an opposing sixth outer edge of the image sensing pixel region.
19 . The integrated chip of claim 12 , wherein the back-side of the substrate within the first pixel region is asymmetric about a line bisecting the first pixel region.
20 . The integrated chip of claim 12 , wherein the first recess and the second recess respectively have a triangular shape in the cross-sectional view.