IP Library Granted Patent US 12,733,556
Granted Patent B2
US 12,733,556 · App. 18/610,104 · Granted Sep 8, 2026

Offset interposers for large-bottom packages and large-die package-on-package structures

Inventors: Russell K. Mortensen (Chandler, AZ); Robert M. Nickerson (Chandler, AZ); Nicholas R. Watts (Phoenix, AZ)
Assignee: Intel Corporation
H10W90/00H05K1/113H05K3/4038H10W70/05H10W70/635H10W70/65H10W72/00H10W72/012H10W72/015H10W72/019H10W72/072H10W72/075H10W72/20H10W72/50H10W72/90H10W90/401H10W90/701H10W70/60H10W72/244H10W72/29H10W72/5363H10W72/5445H10W72/879H10W72/884H10W72/942H10W74/15H10W90/22H10W90/721H10W90/722H10W90/724H10W90/732H10W90/734H10W90/754H10W90/756H10W90/794Y10T29/49124
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Quick Facts
Patent No.
US 12,733,556
App. No.
18/610,104
Granted
Sep 8, 2026
Kind
B2
Abstract

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

Claims (35)

1 . A package, comprising:

a first layer of interconnects;

a second layer of interconnects coupled to the first layer of interconnects, the second layer of interconnects having a through hole therein and an inner edge surrounding the through hole, the second layer of interconnects having a first plurality of conductive pads above a second plurality of conductive pads, and a plurality of conductive vias coupling the first plurality of conductive pads to the second plurality of conductive pads;

an electronic device in the through hole of the second layer of interconnects, the electronic device coupled to the first layer of interconnects, and the electronic device having a lateral width;

a third layer of interconnects over the second layer of interconnects and over the electronic device; and

a die coupled to the third layer of interconnects by a plurality of contacts, the die vertically over the electronic device, the die having a lateral width greater than and covering an entirety of the lateral width of the electronic device, and the die vertically overlapping the second layer of interconnects, wherein one or more of the plurality of contacts are vertically between the die and the second layer of interconnects, and wherein one or more of the plurality of contacts vertically overlaps with the electronic device.

2 . The package of claim 1 , wherein the second layer of interconnects is coupled to the first layer of interconnects by a plurality of solder balls.

3 . The package of claim 1 , wherein the third layer of interconnects is coupled to the second layer of interconnects by a plurality of solder balls.

4 . The package of claim 1 , wherein the second layer of interconnects is coupled to the first layer of interconnects by a first plurality of solder balls, and wherein the third layer of interconnects is coupled to the second layer of interconnects by a second plurality of solder balls.

5 . The package of claim 1 , wherein the lateral width of the die is less than a lateral width of the third layer of interconnects.

6 . A method of fabricating a package, the method comprising:

forming a first layer of interconnects;

forming a second layer of interconnects coupled to the first layer of interconnects, the second layer of interconnects having a through hole therein and an inner edge surrounding the through hole, the second layer of interconnects having a first plurality of conductive pads above a second plurality of conductive pads, and a plurality of conductive vias coupling the first plurality of conductive pads to the second plurality of conductive pads;

providing an electronic device in the through hole of the second layer of interconnects, the electronic device coupled to the first layer of interconnects, and the electronic device having a lateral width;

forming a third layer of interconnects over the second layer of interconnects and over the electronic device; and

coupling a die to the third layer of interconnects by a plurality of contacts, the die vertically over the electronic device, the die having a lateral width greater than and covering an entirety of the lateral width of the electronic device, and the die vertically overlapping the second layer of interconnects, wherein one or more of the plurality of contacts are vertically between the die and the second layer of interconnects, and wherein one or more of the plurality of contacts vertically overlaps with the electronic device.

7 . The method of claim 6 , wherein the second layer of interconnects is coupled to the first layer of interconnects by a plurality of solder balls.

8 . The method of claim 6 , wherein the third layer of interconnects is coupled to the second layer of interconnects by a plurality of solder balls.

9 . The method of claim 6 , wherein the second layer of interconnects is coupled to the first layer of interconnects by a first plurality of solder balls, and wherein the third layer of interconnects is coupled to the second layer of interconnects by a second plurality of solder balls.

10 . The method of claim 6 , wherein the lateral width of the die is less than a lateral width of the third layer of interconnects.

11 . The package of claim 1 , wherein the second layer of interconnects comprises a plurality of interconnects surrounded by a dielectric material, the dielectric material forming the inner edge.

12 . The package of claim 1 , wherein the electronic device has a first height, the second layer of interconnects have a second height, and the first height is no less than the second height.

13 . The package of claim 1 , wherein the second layer of interconnects further comprises an outer edge, and the first plurality of conductive pads and the second plurality of conductive pads are between the inner edge and the outer edge.

14 . The package of claim 1 , wherein, in a cross-section through the first layer of interconnects, the second layer of interconnects, the third layer of interconnects, the electronic device, and the die, the die is vertically overlapping a first portion of the second layer of interconnects on a first side of the electronic device, and the die is vertically overlapping a second portion of the second layer of interconnects on a second side of the electronic device.

15 . The method of claim 6 , wherein the second layer of interconnects comprises a plurality of interconnects surrounded by a dielectric material, the dielectric material forming the inner edge.

16 . The method of claim 6 , wherein the electronic device has a first height, the second layer of interconnects have a second height, and the first height is no less than the second height.

17 . The method of claim 6 , wherein the second layer of interconnects further comprises an outer edge, and the first plurality of conductive pads and the second plurality of conductive pads are between the inner edge and the outer edge.

18 . The method of claim 6 , wherein, in a cross-section through the first layer of interconnects, the second layer of interconnects, the third layer of interconnects, the electronic device, and the die, the die is vertically overlapping a first portion of the second layer of interconnects on a first side of the electronic device, and the die is vertically overlapping a second portion of the second layer of interconnects on a second side of the electronic device.

19 . A package, comprising:

a first layer of interconnects;

an interposer coupled to the first layer of interconnects, the interposer having a through hole therein and an inner edge surrounding the through hole, the interposer having a first plurality of conductive pads above a second plurality of conductive pads, and a plurality of conductive vias coupling the first plurality of conductive pads to the second plurality of conductive pads;

an electronic device in the through hole of the interposer, the electronic device coupled to the first layer of interconnects, and the electronic device having a lateral width;

a second layer of interconnects over the interposer and over the electronic device; and

a die coupled to the second layer of interconnects by a plurality of contacts, the die vertically over the electronic device, and the die having a lateral width greater than and covering an entirety of the lateral width of the electronic device, and the die vertically overlapping the interposer, wherein one or more of the plurality of contacts are vertically between the die and the interposer, and wherein one or more of the plurality of contacts are vertically between the die and the electronic device.

20 . The package of claim 19 , further comprising an underfill surrounding the plurality of contacts, the underfill extending at least across the lateral width of the die.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076007/0292 →
Continuity (6)
Division 17587664 · Jan 28, 2022
Continuation 16679696 · Nov 11, 2019
Continuation 15087153 · Mar 31, 2016
Continuation 14757913 · Dec 24, 2015
Continuation 13977101 · Aug 16, 2011
Related Publication 20240222350A1 · Jul 4, 2024
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