Granted Patent B2

US 12,751,014 · App. 18/613,222 · Granted Sep 29, 2026

Inventors: Shunpei Yamazaki (Setagaya, JP); Tomoaki Atsumi (Hadano, JP); Yuta Endo (Atsugi, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

H10B43/35G11C16/0466G11C16/0483H10B43/27H10B43/40G11C16/10G11C16/26

Abstract

Claims (33)

1 . A semiconductor device comprising:

a substrate; and

a memory cell string comprising a first memory cell over the substrate,

wherein the first memory cell comprises a first transistor,

wherein the first transistor comprises a first gate electrode, a gate insulating layer, a first oxide semiconductor layer, a source electrode, a drain electrode, and a back gate electrode,

wherein a channel formation region of the first transistor is in the first oxide semiconductor layer,

wherein a channel length direction of the first transistor is parallel to a first direction perpendicular to a top surface of the substrate,

wherein a first conductor serving as the first gate electrode faces the channel formation region with the gate insulating layer therebetween,

wherein a second conductor serving as the back gate electrode faces the channel formation, region with an insulator therebetween,

wherein a third conductor serving as the source electrode faces a fourth conductor serving as the drain electrode with the gate insulating layer therebetween,

wherein the third conductor is in contact with a first side surface of the first oxide semiconductor layer,

wherein the fourth conductor is in contact with a second side surface of the first oxide semiconductor layer, and

wherein the second conductor extends in the first direction.

2 . The semiconductor device according to claim 1 , further comprising a silicon transistor,

wherein a channel formation region of the silicon transistor is in the substrate, and

wherein the silicon transistor is electrically connected to the first memory cell.

3 . A semiconductor device comprising:

a substrate;

a prism-like insulator over the substrate; and

a memory cell string comprising a first memory cell on a first side surface of the prism-like insulator and a second memory cell on a second side surface of the prism-like insulator;

wherein the first memory cell comprises a first transistor,

wherein the first transistor comprises a first gate electrode, a gate insulating layer, a first oxide semiconductor layer, a source electrode, a drain electrode, and a back gate electrode,

wherein a channel formation region of the first transistor is in the first oxide semiconductor layer,

wherein a channel length direction of the first transistor is parallel to a first direction perpendicular to a top surface of the substrate,

wherein a first conductor serving as the first gate electrode faces the channel formation region with the gate insulating layer therebetween,

wherein a second conductor serving as the back gate electrode faces the channel formation region with the prism-like insulator therebetween,

wherein a third conductor serving as the source electrode faces a fourth conductor serving as the drain electrode with the gate insulating layer therebetween,

wherein the third conductor is in contact with a first side surface of the first oxide semiconductor layer,

wherein the fourth conductor is in contact with a second side surface of the first oxide semiconductor layer, and

wherein the second conductor extends in the first direction.

4 . The semiconductor device according to claim 3 , further comprising a silicon transistor,

wherein a channel formation region of the silicon transistor is in the substrate, and

wherein the silicon transistor is electrically connected to the first memory cell.

Priority Claims (1)

Continuity (3)

References Cited (359)