IP Library › Assignment 010231/0283
Patent Assignment
Reel/Frame 010231/0283

Assignment of Assignor's Interest

Recorded: 1999-09-22 Pages: 33
Assignor
ATMEL CORPORATION
Executed: 1999-09-13
Assignee
ATMEL CORPORATION
2325 ORCHARD PARKWAY, SAN JOSE, CALIFORNIA, 95131
Covered Properties (201)
Threshold Voltage Control Network for Integrated Circuit Field-Effect Transistors
Patent: 4,435,652 →
Application: 06/267,213 →
Method and Device for Encoding Product and Programming Information in Semiconductors
Patent: 4,451,903 →
Application: 06/303,374 →
Method of Fabricating an Mos Memory Array Having Electrically- Programmable and Electrically-Erasable Storage Devices Incorporated Therein
Patent: 4,490,900 →
Application: 06/343,845 →
Electrically-Programmable and Electrically-Erasable Mos Memory Device
Patent: 4,558,344 →
Application: 06/343,847 →
Method and Device for Providing Process and Test Information in Semiconductors
Patent: 4,419,747 →
Application: 06/346,162 →
Charge Pump for Providing Programming Voltage to the Word Lines in a Semiconductor Memory Array
Patent: 4,511,811 →
Application: 06/346,891 →
Electrical Partitioning Scheme for Improving Yields During the Manufacture of Semiconductor Memory Arrays
Patent: 4,489,401 →
Application: 06/367,332 →
Non-Volatile Memory Cell Fuse Element
Patent: 4,546,454 →
Application: 06/439,602 →
Circuit Chip
Patent: 4,506,139 →
Application: 06/481,542 →
Digital Memory System Utilizing Fast and Slow Address Dependent Access Cycles
Patent: 4,479,180 →
Application: 06/492,367 →
Method of Plasma Etching of Films Containing Chromium
Patent: 4,445,966 →
Application: 06/505,624 →
Step Shape Tailoring by Phase Angle Variation Rf Bias Sputtering
Patent: 4,584,079 →
Application: 06/540,246 →
Fault-Tolerant Memory Array
Patent: 4,768,169 →
Application: 06/546,593 →
Cmos Eprom Sense Amplifier
Patent: 4,725,984 →
Application: 06/581,684 →
Error Checking and Correction Circuitry for Use with an Electrically-Programmable and Electrically-Erasable Memory Array
Patent: 4,612,640 →
Application: 06/581,685 →
Redundancy Circuit for Use in a Semiconductor Memory Array
Patent: 4,617,651 →
Application: 06/582,438 →
Logic Families Interface Circuit and Having a Cmos Latch for Controlling Hysteresis
Patent: 4,558,237 →
Application: 06/595,573 →
Selective Process for Etching Chromium
Patent: 4,498,954 →
Application: 06/597,952 →
Method of Forming a Dielectric Layer Comprising a Gettering Material
Patent: 4,515,668 →
Application: 06/603,858 →
Integrated Circuit Interface
Patent: 4,649,339 →
Application: 06/603,860 →
Interated Circuit Bimetal Layer
Patent: 4,566,026 →
Application: 06/603,862 →
Circuit Chip
Patent: 4,582,975 →
Application: 06/679,855 →
Process for Controlling Mobile Ion Contamination in Semiconductor Devices
Patent: 4,679,308 →
Application: 06/681,768 →
Integrated Schottky Logic Read Only Memory
Patent: 4,661,927 →
Application: 06/691,258 →
Charge Pump for Providing Programming Voltage to the Word Lines in a Semiconductor Memory Array
Patent: 4,673,829 →
Application: 06/699,551 →
Fiber Optic Inspection System
Patent: 4,672,437 →
Application: 06/752,435 →
Programmable, Asynchronous Logic Cell and Array
Patent: 4,700,187 →
Application: 06/803,536 →
Dielectric Barrier Material
Patent: 4,713,682 →
Application: 06/815,426 →
Planarization of Dielectric Layers in Integrated Circuits
Patent: 4,642,162 →
Application: 06/815,603 →
Controlled Mode Field Effect Transistors and Method Therefore
Patent: 4,737,469 →
Application: 06/837,871 →
Apparatus for Page Mode Programming of an Eeprom Cell Array with False Loading Protection
Patent: 4,785,424 →
Application: 06/868,114 →
Block Electrically Erasable Eeprom
Patent: 4,783,766 →
Application: 06/869,207 →
Dielectric Barrier Material
Patent: 4,717,449 →
Application: 06/890,874 →
Programmable Logic Cell and Array
Patent: 4,918,440 →
Application: 06/928,527 →
Mos Floating Gate Memory Cell and Process for Fabricating Same
Patent: 4,701,776 →
Application: 06/936,965 →
Memory Cell with Dual Collector, Active Load Transistors
Patent: 4,754,430 →
Application: 06/943,986 →
Integrated Semiconductor Package
Patent: 4,982,267 →
Application: 07/048,532 →
Mos Floating Gate Memory Cell Containing Tunneling Diffusion Region in Contact with Drain and Extending Under Edges of Field Oxide
Patent: 4,822,750 →
Application: 07/074,085 →
System for Programming Graphically a Programmable, Asynchronous Logic Cell and Array
Patent: 4,845,633 →
Application: 07/076,050 →
Eprom Fabrication Process
Patent: 4,830,974 →
Application: 07/142,641 →
Eeprom Fabrication Process
Patent: 4,833,096 →
Application: 07/145,467 →
Fabrication Process for Eeproms with High Voltage Transistors
Patent: 4,851,361 →
Application: 07/152,313 →
Three Transistor High Endurance Eeprom Cell
Patent: 4,855,955 →
Application: 07/179,527 →
Current-Regulated, Voltage-Regulated Erase Circuit for Eeprom Memory Cells
Patent: 4,888,738 →
Application: 07/212,974 →
Fault Tolerant Differential Memory Cell and Sensing
Patent: 5,029,131 →
Application: 07/212,975 →
Eprom Fabrication Process Forming Tub Regions for High Voltage Device
Patent: 4,859,619 →
Application: 07/219,924 →
Transistor Construction for Low Noise Output Driver
Patent: 4,949,139 →
Application: 07/242,708 →
Reference Voltage Generator
Patent: 4,835,455 →
Application: 07/244,977 →
Output Macrocell for Programmable Logic Device
Patent: 4,894,563 →
Application: 07/256,915 →
Low Power Logic Array Device
Patent: 4,906,870 →
Application: 07/265,830 →
Fluxing Agent
Patent: 4,948,032 →
Application: 07/274,428 →
Memory Cell Circuit with Supplemental Current
Patent: 4,922,411 →
Application: 07/290,386 →
Memory Current Sink
Patent: 4,951,255 →
Application: 07/338,708 →
Differential Switched-Capacitor Sigma-Delta Modulator
Patent: 5,001,725 →
Application: 07/354,654 →
Multiple Part Memory Including Merged Bipolar Transistors
Patent: 5,091,881 →
Application: 07/365,664 →
Programmable Logic Cell and Array
Patent: 5,089,973 →
Application: 07/378,106 →
Memory Input Data Test Arrangement
Patent: 5,077,690 →
Application: 07/391,059 →
Programmable Logic Cell and Array
Patent: 5,019,736 →
Application: 07/427,160 →
Logic Output Control Circuit for a Latch
Patent: 5,023,486 →
Application: 07/502,221 →
Method and an Apparatus for Displaying Graphical Data Received from a Remote Computer by a Local Computer
Patent: 5,210,825 →
Application: 07/514,590 →
Sealed Charge Storage Structure
Patent: 4,970,565 →
Application: 07/522,476 →
Apparatus for Page Mode Programming of an Eeprom Cell Array with False Loading Protection
Patent: 5,101,379 →
Application: 07/551,642 →
Multistage Offset-Cancelled Voltage Comparator
Patent: 5,065,045 →
Application: 07/592,605 →
Method of Forming a Caeeirless Surface Mounted Intergrated Circuit Die
Patent: 5,079,835 →
Application: 07/596,690 →
Programmable Logic Cell and Array
Patent: 5,144,166 →
Application: 07/608,415 →
Programmable and Erasable Mos Memory Device
Patent: 5,066,992 →
Application: 07/609,017 →
Narrow Width Eeprom with Single Diffusion Electrode Formation
Patent: 5,086,325 →
Application: 07/616,460 →
Programmable Logic Device with Global and Local Product Terms
Patent: 5,079,451 →
Application: 07/626,999 →
Gravity-Held Alignment Member for Manufacture of a Leadless Chip Carrier
Patent: 5,085,362 →
Application: 07/642,031 →
Fabricating a Narrow Width Single Diffusion Electrode Formation
Patent: 5,094,968 →
Application: 07/647,308 →
Method of Manufacturing a Repairable Multi-Chip Module
Patent: 5,137,836 →
Application: 07/704,941 →
Programmable Logic Cell and Array
Patent: 5,155,389 →
Application: 07/705,243 →
Apparatus to Transform Time to Frequency and Frequency to Time of Data Signals
Patent: 5,818,742 →
Application: 07/720,202 →
Carrierless Surface Mounted Integrated Circuit Die
Patent: 5,138,115 →
Application: 07/751,319 →
Versatile Programmable Logic Cell for Use in Configurable Logic Arrays
Patent: 5,245,227 →
Application: 07/752,419 →
Clock Selection for Storage Elements of Integrated Circuits
Patent: 5,155,393 →
Application: 07/755,686 →
Programmable Logic Device with Multiple Shared Logic Arrays
Patent: 5,189,320 →
Application: 07/763,921 →
Wireless Communication System
Patent: 5,258,995 →
Application: 07/789,292 →
Method and an Apparatus for Establishing the Functional Capabilities for Wireless Communication Between a Base Unit and a Remote Unit
Patent: 5,267,244 →
Application: 07/789,348 →
Method of Encoding Two Digital Data Signals
Patent: 5,259,003 →
Application: 07/789,731 →
Method and an Apparatus for Re-Establishing Wireless Communication Between a Base Unit and a Remote Unit
Patent: 5,212,808 →
Application: 07/789,736 →
Method and an Apparatus for Establishing a Wireless Communication Link Between a Base Unit and a Remote Unit
Patent: 5,247,702 →
Application: 07/789,737 →
Method and Apparatus for Controlling Transmission Power of a Rremote Unit Communicating with a Base Unit Over a Common Frequency Channel
Patent: 5,278,992 →
Application: 07/790,634 →
Electronic Flasher Unit
Patent: 5,309,142 →
Application: 07/841,415 →
Integrated Logic Circuit with Functionally Flexible Input/Output Macrocells
Patent: 5,231,312 →
Application: 07/850,285 →
Method of Forming Integrated Leadouts for a Chip Carrier
Patent: 5,177,863 →
Application: 07/859,079 →
Bit Level Pipeline Divide Circuit and Method Therefor
Patent: 5,341,322 →
Application: 07/881,336 →
Receiver Having a Local Oscillator First Synchronized to a Reference Frequency and Then to a Received Signal
Patent: 5,283,532 →
Application: 07/894,710 →
Method and Apparatus for Motion Estimation
Patent: 5,430,886 →
Application: 07/898,862 →
Method and Apparatus for Converting Image Data
Patent: 5,359,694 →
Application: 07/919,853 →
Method and Apparatus for Combined Frequency Offset and Timing Offset Estimation
Patent: 5,255,290 →
Application: 07/933,332 →
Programmable Logic Cell and Array with Bus Repeaters
Patent: 5,218,240 →
Application: 07/935,116 →
Method of Forming a Chip Package and Package Interconnects
Patent: 5,216,806 →
Application: 07/939,319 →
High Speed Memory Sense Amplifier with Noise Reduction
Patent: 5,272,674 →
Application: 07/948,481 →
Method for Testing Non-Volatile Memories
Patent: 5,383,193 →
Application: 07/951,207 →
Method of Assembling a Module for a Smart Card
Patent: 5,255,430 →
Application: 07/959,031 →
Voltage Limiting Device Having Improved Gate-Aided Breakdown
Patent: 5,321,292 →
Application: 07/962,123 →
Fabrication Process for Programmable and Erasable Mos Memory Device
Patent: 35,094 →
Application: 07/974,262 →
Integration of High Performance Submicron Cmos and Dual-Poly Non- Volatile Memory Devices Using a Third Polysilicon Layer
Patent: 5,340,764 →
Application: 08/020,291 →
Bumpless Bonding Process Having Multilayer Metallization
Patent: 5,249,728 →
Application: 08/029,148 →
Multiply and Divide Circuit
Patent: 5,270,962 →
Application: 08/031,026 →
Method of Manufacture of an Optoelectronic Coupling Element
Patent: 5,299,727 →
Application: 08/045,665 →
Method and Apparatus for Performing Dct and Idct Transforms on Data Signals with a Pre-Processor, a Post-Processor, and a Controllable Shuffle-Exchange Unit Connected Between the Pre-Processor and Post-Processor
Patent: 5,452,466 →
Application: 08/060,228 →
Method for Forming Thin Tunneling Windows in Eeproms
Patent: 5,352,618 →
Application: 08/100,467 →
Method and Apparatus for Adjusting the Sampling Phase of a Digitally Encoded Signal in a Wireless Communication System
Patent: 5,400,368 →
Application: 08/107,451 →
Method and Apparatus to Determine the Frequency and Time Slot Position in a Digital Wireless Communication Session
Patent: 5,491,726 →
Application: 08/107,938 →
Method of Estimating the Speed of a Mobile Unit in a Digital Wireless Communication System
Patent: 5,438,595 →
Application: 08/108,061 →
Method of Equalizing Digitally Encoded Signals Transmitted in a Plurality of Non-Contiguous Time Slots
Patent: 5,436,942 →
Application: 08/108,084 →
Tab Testing of Area Array Interconnected Chips
Patent: 5,367,763 →
Application: 08/129,753 →
Wireless Communication System
Patent: 5,398,258 →
Application: 08/143,170 →
Wireless Telecommunication Digital Receiver
Patent: 5,479,453 →
Application: 08/174,820 →
Electrostatic Discharge Circuit for High Speed, High Voltage Circuitry
Patent: 5,473,500 →
Application: 08/180,673 →
Breakdown Protection Circuit Using High Voltage Detection
Patent: 5,493,244 →
Application: 08/180,689 →
Stress Reduction for Non-Volatile Memory Cell
Patent: 5,434,815 →
Application: 08/184,227 →
Zero Power High Speed Programmable Circuit Device Architecture
Patent: 5,440,508 →
Application: 08/194,930 →
Core Organization and Sense Amplifier Having Lubricating Current, Active Clamping and Buffered Sense Node for Speed Enhancement for Non-Volatile Memory
Patent: 5,390,147 →
Application: 08/204,866 →
Method and Apparatus for a Wireless Local Area Network
Patent: 5,553,076 →
Application: 08/236,588 →
Parallel Processing Circuit and a Digital Signal Processer Including Same
Patent: 5,442,580 →
Application: 08/248,765 →
Tab Test Device for Area Array Interconnected Chips
Patent: 5,612,514 →
Application: 08/289,884 →
Non-Disruptive, Randomly Addressable Memory System
Patent: 5,488,582 →
Application: 08/296,616 →
Dual Differential Trans-Impedance Sense Amplifier and Method
Patent: 5,493,533 →
Application: 08/313,756 →
Single Layer Polysilicon Eeprom Having Uniform Thickness Gate Oxide/ Capacitor Dielectric Layer
Patent: 5,440,159 →
Application: 08/357,525 →
Input/Output Transistors with Optimized Esd Protection
Patent: 5,493,142 →
Application: 08/397,584 →
Eeprom on Insulator
Patent: 5,656,845 →
Application: 08/400,613 →
Eeprom Array with Flash-Like Core
Patent: 5,606,532 →
Application: 08/405,884 →
Synchronization Apparatus for a Diversity Receiver
Patent: 5,461,646 →
Application: 08/428,848 →
Method and Apparatus for Comparing Data Sets
Patent: 5,504,931 →
Application: 08/438,423 →
Remotely Re-Programmable Program Memory for a Microcontroller
Patent: 5,493,534 →
Application: 08/443,237 →
Programmable Logic Device with Regional and Universal Signal Routing
Patent: 5,594,366 →
Application: 08/492,390 →
Integrated Circuit Contacts with Secured Stringers
Patent: 5,583,380 →
Application: 08/501,503 →
High Speed, Low Voltage Non-Volatile Memory
Patent: 5,587,951 →
Application: 08/511,311 →
Galois Field Polynomial Multiply/Divide Circuit and a Digital Signal Processor Incorporating Same
Patent: 5,602,767 →
Application: 08/521,112 →
Method and Apparatus to Adaptively Control the Frequency of Reception in a Digital Wireless Communication System
Patent: 5,581,579 →
Application: 08/523,032 →
Njthod and Apparatus for Differentiating a Wireless Analog Signal from a Wireless Digitally Encoded Signal
Patent: 5,689,816 →
Application: 08/556,748 →
Digital Signal Processor Optimized for Decoding a Signal Encoded in Accordance with a Viterbi Algorithm
Patent: 5,633,897 →
Application: 08/558,745 →
Circuit for Rotating, Left Shifting, or Right Shifting Bits
Patent: 5,978,822 →
Application: 08/581,047 →
Method and Apparatus for Executing Nested Loops in a Digital Signal Processor
Patent: 5,710,913 →
Application: 08/581,167 →
Digital Signal Processing Method and System Implementing Pipelined Read and Write Operations
Patent: 5,710,914 →
Application: 08/581,320 →
Digital Signal Processing Method and System Employing Separate Program and Data Memories to Store Data
Patent: 5,832,257 →
Application: 08/581,431 →
Non-Disruptive, Randomly Addressable Memory System
Patent: 5,805,503 →
Application: 08/582,516 →
Method and System for Performing Arithmetic Operations with Single or Double Precision
Patent: 5,787,025 →
Application: 08/607,937 →
Signal Processing System with Rom Storing Instructions Encoded for Reducing Power Consumption During Reads and Method for Encoding Such Instructions
Patent: 5,732,255 →
Application: 08/639,780 →
Method of Making a High Voltage Rectifier for an Integrated Circuit Chip
Patent: 5,622,886 →
Application: 08/648,306 →
Field Programmable Gate Array with Distributed Ram and Increased Cell Utilization
Patent: 5,894,565 →
Application: 08/650,477 →
High-Speed, Non-Volatile Electrically Programmable and Erasable Cell and Method
Patent: 5,680,346 →
Application: 08/672,299 →
Voltage to Current Converter for High Frequency Applications
Patent: 5,815,012 →
Application: 08/691,562 →
Clock Feedthrough Reduction System for Switched Current Memory Cells
Patent: 5,783,952 →
Application: 08/714,376 →
Eeprom Array with Flash-Like Core Having Ecc or a Write Cache or Interruptible Load Cycles
Patent: 5,765,185 →
Application: 08/714,605 →
Zero Power Fuse Circuit
Patent: 5,731,734 →
Application: 08/726,956 →
Digital to Analog Converter with Dual Resistor String
Patent: 5,703,588 →
Application: 08/730,592 →
Method and System for Configuring an Array of Logic Devices
Patent: 5,946,219 →
Application: 08/739,606 →
Eight-Bit Microcontroller Having a Risc Architecture
Patent: 5,854,939 →
Application: 08/745,098 →
Oversampled High-Order Modulator
Patent: 5,805,093 →
Application: 08/750,246 →
Music Chip
Patent: 5,905,221 →
Application: 08/786,283 →
Bitline Load and Precharge Structure for an Sram Memory
Patent: 5,781,469 →
Application: 08/788,523 →
Dual Buffer Flash Memory Architecture with Multiple Operating Modes
Patent: 5,822,245 →
Application: 08/824,175 →
Eight-Bit Microcontroller Having a Risc Architecture
Patent: 5,809,327 →
Application: 08/824,932 →
Combined Program and Data Nonvolatile Memory with Concurrent Program-Read/Data Write Capability
Patent: 5,732,017 →
Application: 08/829,378 →
A Memory Device Having a Power Supply-Independent Low Power Comsump Tion Bit Line Voltage Clamp
Patent: 5,828,603 →
Application: 08/842,008 →
Floating Gate Memory Cell with Charge Leakage Prevention
Application: 08/853,691 →
Semiconductor Memory Having a Current Balancing Circuit
Patent: 5,917,754 →
Application: 08/859,885 →
Digital Circuit Using Memory for Monitoring Signals for Occurrences of Predefined Breakpoint Conditions
Patent: 5,931,956 →
Application: 08/872,822 →
Universal Serial Bus Device Controller Comprising a Fifo Associated with a Plurality of Endpoints and a Memory for Storing an Identifier of a Current Endpoint
Patent: 5,974,486 →
Application: 08/909,988 →
High Impedance Bias Circuit for Ac Signal Amplifiers
Patent: 5,949,274 →
Application: 08/935,405 →
Fpga Logic Cell Internal Structure Including Pair of Look-Up Tables
Patent: 6,026,227 →
Application: 08/936,334 →
Field Programmable Gate Array Having Access to Orthogonal and Diagonal Adjacent Neighboring Cells
Patent: 6,014,509 →
Application: 08/937,105 →
Modulation Compensated Clamp Circuit
Patent: 5,815,355 →
Application: 08/944,321 →
Fast Regular Multiplier Architecture
Patent: 6,029,187 →
Application: 08/959,245 →
Boundary Scan System with Address Dependent Instructions
Patent: 6,032,279 →
Application: 08/965,919 →
Memory Device Having Programmable Access Protection and Method of Operating the Same
Patent: 5,974,500 →
Application: 08/971,117 →
Zero-Delay Slew-Rate Controlled Output Buffer
Patent: 5,949,259 →
Application: 08/974,579 →
Zero Power Power-on Reset Circuit
Patent: 5,936,444 →
Application: 08/977,779 →
Zero Power High Speed Configuration Memory
Patent: 5,946,267 →
Application: 08/978,286 →
Integrated Circuit with Flag Register for Block Selection of Nonvolatile Cells for Bulk Operations
Patent: 5,848,026 →
Application: 08/986,506 →
Minimum Voltage Radio Frequency Indentification
Patent: 5,945,920 →
Application: 08/988,504 →
Nrequency Synthesis Circuit Tuned by Digital Words
Patent: 5,977,805 →
Application: 09/010,434 →
Method of Communication Between a Plurality of Remote Units and a Control Unit
Patent: 6,104,279 →
Application: 09/046,374 →
Leadless Array Package
Patent: 6,177,722 →
Application: 09/063,817 →
Configuration Control in a Programmable Logic Device Using Non-Volatile Elements
Patent: 5,968,196 →
Application: 09/063,872 →
Sense Amplifier with Zero Power Idle Mode
Patent: 5,963,496 →
Application: 09/064,811 →
Crystal Oscillator with Controlled Duty Cycle
Patent: 6,028,491 →
Application: 09/069,696 →
Microcontroller Including a Single Memory Module Having a Data Memory Sector and a Code Memory Sector and Supporting Simultaneous Read/Write Access to Both Sectors
Patent: 6,032,248 →
Application: 09/069,884 →
Method and Apparatus for a Serial Access Memory
Patent: 6,038,185 →
Application: 09/076,751 →
Fpga Structure Having Main, Column and Sector Clock Lines
Patent: 6,167,559 →
Application: 09/078,409 →
Circuit for Transferring High Voltage Video Signal Without Signal Loss
Patent: 6,140,993 →
Application: 09/097,866 →
Digital Sound-Producing Integrated Circuit with Virtual Cache
Patent: 5,918,302 →
Application: 09/148,437 →
Method of Forming Interconnects Using Selective Deposition
Application: 09/154,801 →
Fuse Circuit Having Zero Power Draw for Partially Blown Condition
Patent: 5,999,038 →
Application: 09/160,526 →
Integration of High Performance Submicron Cmos and Dual-Poly Non-Volatile Memory Devices Using a Third Polysilicon Layer
Patent: 36,777 →
Application: 09/167,919 →
Integrated Audio Mixer
Patent: 6,154,161 →
Application: 09/168,223 →
Dual Read Protocols for an External Memory in a Microcontroller Environment
Application: 09/183,617 →
Boundary Scan Method for Terminating or Modifying Integrated Circuit Operating Modes
Patent: 6,158,034 →
Application: 09/205,651 →
Method for Constructing a Leadless Array Package
Patent: 6,004,833 →
Application: 09/216,019 →
Reducing Digital Switching Noise in Mixed Signal Ic's
Patent: 6,215,432 →
Application: 09/262,717 →
Microprocessing Device Having Programmable Wait States
Patent: 6,356,987 →
Application: 09/266,045 →
Apparatus and Method for an Integrated Circuit Having High Q Reactive Components
Patent: 6,218,729 →
Application: 09/267,889 →
Signal Processing Method and Device
Patent: 6,600,789 →
Application: 09/319,232 →
Digital Automatic Gain Control
Patent: 6,122,331 →
Application: 09/332,932 →
Method and Apparatus for Testing a Video Display Chip
Patent: 6,115,305 →
Application: 09/333,805 →
Fabrication Process for Dishing-Free Cu Damascene Structures
Application: 09/352,545 →
Publication: US 2001/0051431
Method for Reading Out the Contents of a Serial Memory
Patent: 6,097,657 →
Application: 09/384,823 →
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignors Interest. May 26, 1981
From: STEVENS, EMSLEY H.
To: HONEYWELL INC., A CORP. OF DE.
Reel/Frame 003891/0044 →
Assignment of Assignors Interest. Mar 30, 1982
From: PERLEGOS, GEORGE
To: SEEQ TECHNOLOGY, LINC.
Reel/Frame 003967/0143 →
Assignment of Assignors Interest. Mar 30, 1982
From: JORDAN, LARRY T.
To: SEEZ TECHNOLOGY, INC.
Reel/Frame 003967/0152 →
Assignment of Assignors Interest. Mar 30, 1982
From: GUPTA, ANIL
To: SEEQ TECHNOLOGY, INC.
Reel/Frame 003967/0150 →
Assignment of Assignors Interest. Mar 30, 1982
From: CHIU, TE-LONG
To: SEEQ TECHNOLOGY, INC.
Reel/Frame 003967/0148 →
Assignment of Assignors Interest. Apr 12, 1982
From: SMARANDOIU, GEORGE; PERLEGOS, GEORGE
To: SEEQ TECHNOLOGY, INC.
Reel/Frame 004004/0781 →
Assignment of Assignors Interest. Sep 1, 1982
From: JORDAN, LARRY T.
To: SEEQ TECHNOLOGY,INC., A CORP OF CA
Reel/Frame 004029/0940 →
Assignment of Assignors Interest. Nov 5, 1982
From: GUPTA, ANIL; PERLEGOS, GEORGE
To: SEEQ TECHNOLOGY, INC.
Reel/Frame 004068/0994 →
Assignment of Assignors Interest. Apr 4, 1983
From: DAUGHTON, JAMES M.
To: HONEYWELL INC.
Reel/Frame 004114/0077 →
Assignment of Assignors Interest. Jun 20, 1983
From: CARLSON, ROBERT J.; YOUNGNER, DANIEL W.
To: HONEYWELL INC.
Reel/Frame 004158/0871 →
Assignment of Assignors Interest. Oct 28, 1983
From: PERLEGOS, GEORGE
To: SEEQ TECHNOLOGY, INC.
Reel/Frame 004189/0642 →
Assignment of Assignors Interest. Dec 9, 1983
From: LEE, EDDIE C.; NUNNE, WILLIAM H.
To: HONEYWELL INC., MINNEAPOLIS, MN A CORP.
Reel/Frame 004198/0213 →
Assignment of Assignors Interest. Mar 30, 1984
From: RABE, ROBERT L.; SWAN, PAUL J.
To: HONEYWELL INC., A CORP OF DE
Reel/Frame 004259/0611 →
Assignment of Assignors Interest. Apr 9, 1984
From: HUSTON, DENNIS L.; KARDASHIAN, VAHRAM S.; MONES, ARTHUR H.
To: HONEYWELL INC., A CORP OF DE
Reel/Frame 004248/0310 →
Assignment of Assignors Interest. Apr 25, 1984
From: BROWNELL, DAVID J.; ROBERTS, JON A.
To: HONEYWELL INC., MINNEAPOLIS, MN A DE CORP.
Reel/Frame 004254/0455 →
Assignment of Assignors Interest. Apr 25, 1984
From: LEE, ED C.; ROBERTS, JON A.
To: HONEYWELL INC., MINNEAPOLIS, MN A DE CORP.
Reel/Frame 004254/0447 →
Assignment of Assignors Interest. Apr 25, 1984
From: GRANGROTH, ROBERT H.; LOY, JERALD M.
To: HONEYWELL INC., MINNEAPOLIS, MN A DE CORP.
Reel/Frame 004254/0450 →
Assignment of Assignors Interest. Dec 14, 1984
From: FINN, CHRIS J.; YOUNGNER, DANIEL W.
To: HONEYWELL INC.
Reel/Frame 004350/0177 →
Assignment of Assignors Interest. Apr 29, 1985
From: IP, WILLIAM W.; PERLEGOS, GUST
To: SEEQ TECHNOLOGY, INC. A CORP OF CA
Reel/Frame 004391/0937 →
Assignment of Assignors Interest. May 6, 1985
From: MEHROTRA, SANJAY; PERLEGOS, GUST
To: SEEQ TECHNOLOGY, INC. A CORP OF CA
Reel/Frame 004395/0977 →
Assignment of Assignors Interest. Apr 14, 1989
From: HOBBS, JAMES B.
To: HONEYWELL INC., A CORP. OF DE
Reel/Frame 005064/0311 →
Assignment of Assignors Interest. Dec 29, 1989
From: HONEYWELL INC.
To: ATMEL CORPORATION
Reel/Frame 005258/0088 →
Assignment of Assignors Interest. Dec 29, 1989
From: HONEYWELL INC.
To: ATMEL CORPORATION, A CA CORP.
Reel/Frame 005224/0010 →
Assignment of Assignors Interest. Aug 13, 1990
From: WESTINGHOUSE ELECTRIC CORPORATION
To: ATMEL CORPORATION, A CORP. OF CA
Reel/Frame 005399/0122 →
Assignment of Assignors Interest. Feb 26, 1992
From: FRITZ, ANDREAS
To: TELEFUNKEN ELECTRONIC GMBH
Reel/Frame 006029/0705 →