Wafer carrier having thermal cover for chemical vapor deposition systems
View Patent ↗The invention relates generally to semiconductor fabrication technology and, more particularly, to chemical vapor deposition (CVD) processing and associated apparatus for addressing temperature non-uniformities on semiconductor wafer surfaces. Embodiments include a wafer carrier for use in a system for growing epitaxial layers on one or more wafers by CVD, the wafer carrier comprising a top plate and base plate which function coordinately to reduce temperature variability caused during CVD processing.
1. A wafer carrier for use in a system for growing epitaxial layers on one or more wafers by chemical vapor deposition (CVD), the wafer carrier comprising:
a top plate made of a plurality of pieces, wherein:
a plurality of shapes each corresponding to an exposed area of the wafer carrier that is not below the top plate are defined by two or more of the plurality of pieces,
each one of the plurality of pieces is not in direct contact with any other of the plurality of pieces, and
the plurality of pieces are arranged to reduce temperature non-uniformities during epitaxial growth; and
a base plate, wherein the base plate includes surface portions arranged to support each of a plurality of wafers adjacent the exposed areas defined by the top plate, and wherein the plurality of pieces that make up the top plate are removably secured to cover areas of the base plate not covered by the plurality of wafers, such that a relative arrangement of the base plate, top plate, and the plurality of wafers produces a more uniform thermal insulating characteristic over the surface of each one of the plurality of wafers during CVD processing compared to an arrangement lacking the top plate.
2. The wafer carrier of claim 1 , wherein the top plate is constructed and arranged to provide thermal insulating characteristics over the surface of the bottom plate that are equivalent to those of the wafers.
3. The wafer carrier of claim 1 , wherein the top plate is constructed from a material having different thermal properties than the plurality of wafers.
4. The wafer carrier of claim 1 , wherein the top plate is constructed to have a different thickness than the plurality of wafers.
5. The wafer carrier of claim 1 , wherein the top plate is arranged at different vertical spacing relative to the bottom plate than the plurality of wafers.
6. The wafer carrier of claim 1 , wherein the top plate comprises a similar material as the plurality of wafers.
7. The wafer carrier of claim 1 , wherein the top plate comprises at least one ceramic material selected from the group consisting of: quartz, silicon carbide, solid silicon carbide, aluminum nitride, boron nitride, boron carbide, alumina.
8. The wafer carrier of claim 1 , wherein the top plate and the plurality of wafers are situated along a common horizontal plane.
9. The wafer carrier of claim 1 , wherein the top plate and the plurality of wafers are situated at a common vertical distance from the base plate.
10. The wafer carrier of claim 1 , wherein the top plate and the plurality of wafers rest on tabs extending from the base plate, such that a gap distance between the plurality of wafers and a top surface of the base plate situated beneath each of the plurality of wafers is equivalent to a gap distance between the top plate and the top surface of the base plate.
11. The wafer carrier of claim 1 , wherein the top plate and the plurality of wafers are in the same horizontal plane and wherein the top plate and the plurality of wafers are in direct contact.
12. The wafer carrier of claim 1 , wherein the top plate and the plurality of wafers are in a common horizontal plane and wherein the top plate and each of the plurality of wafers are in a non-contact arrangement relative to one another.
13. The wafer carrier of claim 1 , wherein the top plate and the base plate are fastened together using a plurality of mechanical fasteners.
14. The wafer carrier of claim 1 , wherein the top plate and the base plate are arranged to collectively form a wafer pocket defining a peripheral wall that surrounds the circumference of each wafer.