Processed stacked dies
Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.
1. A method for forming a microelectronic system, comprising:
singulating a plurality of semiconductor die components from a wafer component, the semiconductor die components each having a substantially planar surface;
removing particles and shards of material from edges of the plurality of semiconductor die components;
etching the substantially planar surface of the plurality of semiconductor die components to a preselected depth or for a preselected duration; and
bonding one or more of the plurality of semiconductor die components to a prepared bonding surface, via the substantially planar surface.
2. The method for forming a microelectronic system of claim 1 , further comprising etching the edges of the plurality of semiconductor die components to remove the particles and shards from the edges of the plurality of semiconductor die components.
3. The method for forming a microelectronic system of claim 2 , further comprising etching the edges of the plurality of semiconductor die components while the plurality of semiconductor die components are on a dicing carrier.
4. The method for forming a microelectronic system of claim 2 , further comprising etching the edges of the plurality of semiconductor die components using a chemical etchant comprising hydrofluoric acid and nitric acid with Benzotriazole (BTA).
5. The method for forming a microelectronic system of claim 2 , further comprising etching the edges of the plurality of semiconductor die components using a plasma etch.
6. The method for forming a microelectronic system of claim 2 , further comprising etching the edges of the plurality of semiconductor die components to reduce a thickness of the plurality of semiconductor die components such that a space is created at one or more of the edges of each of the plurality of semiconductor die components.
7. The method for forming a microelectronic system of claim 2 , wherein the semiconductor die components include an oxide layer as the substantially planar surface, and wherein the etching includes removing at least a portion of the oxide layer at the edges of the plurality of semiconductor die components.
8. The method for forming a microelectronic system of claim 2 , further comprising applying a protective coating to the substantially planar surface of the plurality of semiconductor die components prior to the etching to protect the substantially planar surface from an etchant.
9. The method for forming a microelectronic system of claim 8 , further comprising:
heating the plurality of semiconductor die components after singulating to cause the protective coating to recede from a periphery of the plurality of semiconductor die components; and
etching the periphery of the plurality of semiconductor die components to a preselected depth.
10. The method for forming a microelectronic system of claim 9 , wherein the plurality of semiconductor die components comprises a dielectric layer over a base semiconductor layer, wherein the etching the periphery of the plurality of semiconductor die components includes removing the dielectric layer and exposing the base semiconductor layer at the periphery of the plurality of semiconductor die components.
11. The method for forming a microelectronic system of claim 10 , further comprising removing a portion of the base semiconductor layer in addition to the dielectric layer at the periphery of the plurality of semiconductor die components.
12. The method for forming a microelectronic system of claim 11 , further comprising forming an undercut at a periphery of the base semiconductor layer, such that an area of the base semiconductor layer is less than an area of a footprint of the dielectric layer.
13. The method for forming a microelectronic system of claim 12 , further comprising forming an undercut at a periphery of the prepared bonding surface, such that an area of the prepared bonding surface is less than an area of a footprint of the dielectric layer.
14. The method for forming a microelectronic system of claim 10 , further comprising forming an undercut at a periphery of the dielectric layer, such that an area of the dielectric layer is less than an area of a footprint of the base semiconductor layer.
15. The method for forming a microelectronic system of claim 8 , wherein the protective coating comprises a resist layer that is patterned to expose at least the periphery of the plurality of semiconductor die components.
16. The method for forming a microelectronic system of claim 1 , wherein the one or more of the plurality of semiconductor die components are bonded using either a direct bonding technique without adhesive or a metal to metal diffusion bond.
17. The method for forming a microelectronic system of claim 1 , further comprising removing particles and shards of material from a sidewall of the plurality of semiconductor die components, wherein the particles and shards are removed from the sidewall by etching the sidewall of the plurality of semiconductor die components.
18. The method for forming a microelectronic system of claim 1 , further comprising coating particles and shards of material to a sidewall of the plurality of semiconductor die components, wherein the particles and shards are coated to the sidewall by depositing a coating layer onto the sidewall of the plurality of semiconductor die components.
19. The method for forming a microelectronic system of claim 18 , further comprising spin coating or electrocoating the sidewall of the plurality of semiconductor die components with a glass, a boron doped glass, or a phosphorus doped glass.
20. The method for forming a microelectronic system of claim 19 , further comprising heat curing the glass, the boron doped glass, or the phosphorus doped glass to the sidewall of the plurality of semiconductor die components.
21. A method for forming a microelectronic system, comprising:
singulating a plurality of semiconductor die components from a wafer component, the semiconductor die components each comprising a dielectric layer over a base semiconductor layer and having a substantially planar surface;
etching the periphery of the plurality of semiconductor die components to a preselected depth or for a preselected duration, including removing at least a portion of the dielectric layer at the periphery of the plurality of semiconductor die components; and
bonding one or more of the plurality of semiconductor die components to a prepared bonding surface, via the substantially planar surface.