Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias
A semiconductor device and method of manufacture are presented in which a first semiconductor device and second semiconductor device are bonded to a first wafer and then singulated to form a first package and a second package. The first package and second package are then encapsulated with through interposer vias, and a redistribution structure is formed over the encapsulant. A separate package is bonded to the through interposer vias.
1. A method of manufacturing a semiconductor device, the method comprising:
attaching a first semiconductor device and a second semiconductor device to a first wafer;
forming first through interposer vias adjacent to the first semiconductor device and the second semiconductor device;
exposing through substrate vias by removing a portion of the first semiconductor device and the second semiconductor device;
applying a dielectric material around the first through interposer vias;
singulating the first wafer to form a first package and a second package;
attaching the first package and the second package to a carrier wafer, wherein second through interposer vias are located on the carrier wafer;
encapsulating the first package, the second package, and the second through interposer vias with an encapsulant;
thinning the encapsulant to expose the through substrate vias; and
forming a redistribution structure over the encapsulant.
2. The method of claim 1 , wherein the attaching the first semiconductor device and the second semiconductor device forms a hybrid bond.
3. The method of claim 1 , further comprising thinning the first semiconductor device after the attaching the first semiconductor device and prior to the forming the first through interposer vias.
4. The method of claim 1 , wherein the exposing the through substrate vias is performed prior to the applying the dielectric material.
5. The method of claim 1 , wherein the exposing the through substrate vias is performed after the applying the dielectric material.
6. The method of claim 5 , further comprising applying a second dielectric material around the through substrate vias after the exposing the through substrate vias.
7. The method of claim 6 , further comprising planarizing the second dielectric material to be coplanar with the dielectric material.
8. A method of manufacturing a semiconductor device, the method comprising:
attaching a first die and a second die to a first wafer, the first die comprising first through substrate vias;
thinning the first die and the second die without exposing the first through substrate vias;
forming first through interposer vias on the first wafer after the thinning the first die and the second die;
applying a dielectric material around the first die, the second die, and the first through interposer vias;
singulating the first wafer to form a first package and a second package;
encapsulating the first package, the second package, and second through interposer vias with an encapsulant;
thinning the encapsulant to expose the first through substrate vias;
recessing a portion of the first die and a portion of the second die after the thinning the encapsulant;
applying a second dielectric material into the recess; and
forming a redistribution structure over the second dielectric material.
9. The method of claim 8 , wherein the first package and the second package are attached to a polymer layer prior to the encapsulating the first package, the second package, and the second through interposer vias.
10. The method of claim 9 , further comprising forming an opening through the polymer layer.
11. The method of claim 10 , further comprising attaching a third package to the second through interposer vias through the opening in the polymer layer.
12. The method of claim 8 , wherein the attaching the first die and the second die is performed at least in part through a hybrid bonding process.
13. The method of claim 8 , wherein the attaching the first die is performed by bonding a first bond metal of the first die to a second bond metal of the first wafer, the first bond metal being within a first metallization layer.
14. The method of claim 8 , further comprising planarizing the second dielectric material at least until the second dielectric material is coplanar with the dielectric material.
15. A method of manufacturing a semiconductor device, the method comprising:
thinning a first die and a second die without exposing first through substrate vias within the first die, wherein the first die is hybrid bonded to a first wafer prior to the thinning the first die;
plating first through interposer vias onto the first wafer after the thinning the first die and the second die;
forming a first package from the first die and the first wafer;
forming a second package from the second die and the first wafer;
plating second through interposer vias onto a carrier wafer;
encapsulating the first package, the second package, and the second through interposer vias with an encapsulant, wherein the encapsulant is in physical contact with the first through interposer vias;
planarizing the encapsulant to expose the first through substrate vias;
exposing sidewalls of the first through substrate vias by removing a portion of the first die after the planarizing the encapsulant; and
replacing the portion of the first die with a dielectric material.
16. The method of claim 15 , further comprising planarizing the dielectric material until the dielectric material is coplanar with the encapsulant.
17. The method of claim 15 , further comprising:
forming a redistribution structure over the dielectric material: and
attaching a surface device to the redistribution structure.
18. The method of claim 15 , further comprising attaching the first package and the second package to a polymer layer on the carrier wafer prior to the encapsulating the first package, the second package, and the second through interposer vias.
19. The method of claim 18 , further comprising attaching a third package to the second through interposer vias through the polymer layer.
20. The method of claim 15 , further comprising bonding a first bond metal of the first die to a second bond metal of the first wafer and bonding a first dielectric layer of the first die to a second dielectric layer of the first wafer, the first bond metal being within a first metallization layer.