3D chip with shared clock distribution network
Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.
1. A three-dimensional (3D) circuit comprising:
a first integrated circuit (IC) die comprising a first semiconductor substrate and a first set of interconnect layers defined on the first semiconductor substrate, at least one interconnect layer of the first IC die comprising a first set of clock interconnect segments; and
a second IC die comprising a second semiconductor substrate and a second set of interconnect layers defined on the second semiconductor substrate, at least one interconnect layer of the second IC die comprising a second set of clock interconnect segments, the second IC die face-to-face mounted with the first IC die that places the top interconnect layer of the first IC die next to the top interconnect layer of the second IC die; and
a plurality of direct-bonded connections to connect clock interconnect segments in the first set of clock interconnect segments with clock interconnect segments in the second set of clock interconnect segments, in order to connect the first and second sets of clock interconnect segments to define a clock distribution network for the first and second IC dies.
2. The 3D circuit of claim 1 , wherein the first set of clock interconnect segments are on the top interconnect layer of the first IC die, and the second set of clock interconnect segments are on the top interconnect layer of the second IC die.
3. The 3D circuit of claim 2 , wherein positioning the first and second sets of clock interconnect segments on the top interconnect layers of the first and second IC dies shields the clock distribution network from signals outside of the 3D chip as the positioning places the clock distribution network within the interior of an interconnect layer vertical stack formed by the first and second sets of interconnect layers.
4. The 3D circuit of claim 1 , wherein the direct-bonded connections are native connections that allow signals to span the first and second IC dies without passing through any intervening circuit.
5. The 3D circuit of claim 1 , wherein the direct-bonded connections allow native signals from one IC die to pass to the other IC die without any modifications.
6. The 3D circuit of claim 5 , wherein the native signals do not traverse through input/output circuits to pass from one IC die to the other IC die.
7. The 3D circuit of claim 1 , wherein the first and second sets of clock interconnect segments are thicker and wider than clock interconnect segments on a set of interconnect layers that are lower than the interconnect layers of the first and second sets of clock interconnect segments.
8. The 3D circuit of claim 7 , wherein the thicker and wider first and second sets of clock interconnect segments have lower resistance and suffer less signal degradation than narrower interconnect segments on the set of interconnect layers that are below the interconnect layers of the first and second sets of clock interconnect segments, wherein the lower resistance allows a clock signal to be driven a longer distance on the interconnect layers that comprise the first and second sets of clock interconnect segments.
9. The 3D circuit of claim 1 , wherein the clock distribution network is a clock distribution tree.
10. The 3D circuit of claim 9 , wherein the clock distribution tree is an H-tree.
11. The 3D circuit of claim 9 , wherein
the first set of clock interconnect segments of the first IC die comprises vertical clock interconnect segments,
the second set of clock interconnect segments of the second IC die comprises horizontal clock interconnect segments,
each of a plurality of direct-bonded connections connect a pair of clock interconnect segments that includes one vertical clock interconnect segment of the first set and one horizontal clock interconnect segment of the second set.
12. The 3D circuit of claim 1 , wherein the direct-bonded connections are defined through a direct-bonding process that face-to-face mounts the first and second IC dies.
13. The 3D circuits of claim 1 , wherein the direct-bonded connections are 10 microns or shorter.
14. An electronic device comprising:
a three-dimensional (3D) circuit comprising:
a first integrated circuit (IC) die comprising a first semiconductor substrate and a first set of interconnect layers defined on the first semiconductor substrate, at least one interconnect layer of the first IC die comprising a first set of clock interconnect segments; and
a second IC die comprising a second semiconductor substrate and a second set of interconnect layers defined on the second semiconductor substrate, at least one interconnect layer of the second IC die comprising a second set of clock interconnect segments, the second IC die face-to-face mounted with the first IC die that places the top interconnect layer of the first IC die next to the top interconnect layer of the second IC die; and
a plurality of direct-bonded connections to connect clock interconnect segments in the first set of clock interconnect segments with clock interconnect segments in the second set of clock interconnect segments, in order to connect the first and second sets of clock interconnect segments to define a clock distribution network for the first and second IC dies; and
another substrate on which the 3D circuit is mounted.
15. The electronic device of claim 14 , wherein the first set of clock interconnect segments are on the top interconnect layer of the first IC die, and the second set of clock interconnect segments are on the top interconnect layer of the second IC die.
16. The electronic device of claim 15 , wherein positioning the first and second sets of clock interconnect segments on the top interconnect layers of the first and second IC dies shields the clock distribution network from signals outside of the 3D chip as the positioning places the clock distribution network within the interior of an interconnect layer vertical stack formed by the first and second sets of interconnect layers.
17. The electronic device of claim 14 , wherein the direct-bonded connections are native connections that allow signals to span the first and second IC dies without passing through any intervening circuit.
18. The electronic device of claim 14 , wherein the first and second sets of clock interconnect segments are thicker and wider than interconnect segments on a set of interconnect layers that are below the interconnect layers that comprise the first and second sets of clock interconnect segments.
19. The electronic device of claim 18 , wherein the thicker and wider first and second sets of clock interconnect segments have lower resistance and suffer less signal degradation than narrower interconnect segments on the set of interconnect layers that are lower than the interconnect layers of the first and second sets of clock interconnect segments, wherein the lower resistance allows a clock signal to be driven a longer distance on the clock distribution network.
20. The electronic device of claim 14 , wherein the clock distribution network is a clock distribution tree.