Ferroelectric memory device and method of forming the same
Provided is a ferroelectric memory device having a dielectric layer vertically interleaved between a first conductive line and a second conductive line. A first ferroelectric portion is arranged along a sidewall of the first conductive line and a second ferroelectric portion is arranged along a sidewall of the second conductive line. A channel layer is arranged along sides of the dielectric layer, the first conductive line, and the second conductive line. A topmost surface of the first ferroelectric portion is vertically separated from a bottommost surface of the second ferroelectric portion by the channel layer.
1 . A ferroelectric memory device, comprising:
a dielectric layer vertically interleaved between a first conductive line and a second conductive line;
a first ferroelectric portion arranged along a sidewall of the first conductive line;
a second ferroelectric portion arranged along a sidewall of the second conductive line; and
a channel layer arranged along sides of the dielectric layer, the first conductive line, and the second conductive line, wherein a topmost surface of the first ferroelectric portion is vertically separated from a bottommost surface of the second ferroelectric portion by the channel layer, wherein the channel layer includes a horizontally extending surface that is vertically and directly between the first ferroelectric portion and the second ferroelectric portion.
2 . The ferroelectric memory device of claim 1 , wherein the topmost surface of the first ferroelectric portion laterally extends between opposing outermost sidewalls of the first ferroelectric portion.
3 . The ferroelectric memory device of claim 1 , further comprising:
a conductive pillar vertically extending past the first ferroelectric portion and the second ferroelectric portion, wherein the conductive pillar has a wavy sidewall.
4 . The ferroelectric memory device of claim 1 , wherein the first conductive line contacts the first ferroelectric portion along a vertical interface continuously extending between the topmost surface and a bottommost surface of the first ferroelectric portion.
5 . The ferroelectric memory device of claim 1 , wherein the channel layer has an outermost sidewall contacting the dielectric layer.
6 . The ferroelectric memory device of claim 5 , wherein the outermost sidewall has a height that is substantially equal to a height of the dielectric layer.
7 . The ferroelectric memory device of claim 1 , further comprising:
a conductive pillar vertically extending past the first ferroelectric portion and the second ferroelectric portion, wherein the channel layer has a first outermost sidewall contacting the conductive pillar and a second opposing outermost sidewall contacting the dielectric layer.
8 . A ferroelectric memory device, comprising:
a plurality of dielectric layers vertically interleaved between a plurality of conductive lines;
a plurality of data storage structures arranged on sidewalls of the plurality of conductive lines;
a channel layer arranged along sides of the plurality of conductive lines and the plurality of dielectric layers, wherein the channel layer is laterally separated from the plurality of conductive lines by the plurality of data storage structures; and
a conductive pillar laterally separated from the plurality of conductive lines and the plurality of dielectric layers by the channel layer, wherein the conductive pillar has a plurality of protrusions extending outward from a sidewall of the conductive pillar, the channel layer conformally covering the plurality of protrusions.
9 . The ferroelectric memory device of claim 8 , further comprising:
an isolation pillar neighboring the conductive pillar along a first direction, wherein the conductive pillar is separated from the plurality of conductive lines along a second direction that is perpendicular to the first direction, as viewed in a plan-view.
10 . The ferroelectric memory device of claim 9 , wherein the isolation pillar contacts the conductive pillar and the channel layer along the first direction.
11 . The ferroelectric memory device of claim 10 , wherein the isolation pillar laterally contacts the plurality of data storage structures along the second direction.
12 . The ferroelectric memory device of claim 8 , wherein the plurality of data storage structures respectively include a ferroelectric material.
13 . The ferroelectric memory device of claim 8 , wherein an outermost sidewall of one of the plurality of data storage structures completely covers an outermost sidewall of one of the plurality of conductive lines.
14 . The ferroelectric memory device of claim 8 , wherein a first conductive line of the plurality of conductive lines is substantially symmetric about a vertical line bisecting the first conductive line.
15 . A ferroelectric memory device, comprising:
a plurality of dielectric layers vertically interleaved between a plurality of conductive lines over a substrate;
a channel layer arranged along sides of the plurality of conductive lines and the plurality of dielectric layers; and
a plurality of data storage structures arranged along sidewalls of the plurality of conductive lines, wherein the channel layer is laterally separated from the plurality of conductive lines by the plurality of data storage structures and wherein the channel layer comprises a winding structure including a plurality of protrusions extending outward from a sidewall of the channel layer in a direction of closest ones of the plurality of dielectric layers, the plurality of data storage structures being disposed vertically between neighboring ones of the plurality of protrusions.
16 . The ferroelectric memory device of claim 15 , wherein the sidewall of the channel layer is laterally separated from one of the plurality of conductive lines by one of the plurality of data storage structures, the sidewall being directly over an underlying part of the channel layer.
17 . The ferroelectric memory device of claim 15 , wherein the plurality of data storage structures are completely confined within recesses in a side of the channel layer.
18 . The ferroelectric memory device of claim 15 , wherein an outermost sidewall of the channel layer laterally contacts the plurality of dielectric layers.
19 . The ferroelectric memory device of claim 15 , wherein the plurality of data storage structures include a first data storage structure, the first data storage structure having an outermost sidewall covering an entirety of one of the plurality of conductive lines.
20 . The ferroelectric memory device of claim 15 , wherein the plurality of protrusions are at same heights over the substrate as the plurality of dielectric layers.